Re: [PATCH v1 1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD

LGTM 於 2024年9月20日 週五 10:19 寫道： > From: Pan Li > > This patch would like to add testcases of the signed scalar SAT_ADD > for form 3. Aka: > > Form 3: > #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ > T __attribute__((noinline))\ > sat_s_add_##T##_fmt

[PATCH v1 1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD

From: Pan Li This patch would like to add testcases of the signed scalar SAT_ADD for form 3. Aka: Form 3: #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ T __attribute__((noinline))\ sat_s_add_##T##_fmt_3 (T x, T y) \ {