Committed, thanks Juzhe.
Pan
From: 钟居哲
Sent: Friday, September 1, 2023 3:28 PM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode
LGTM。
juzhe.zh...@rivai.ai
LGTM。
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-09-01 11:33
To: gcc-patches
CC: juzhe.zhong; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Support FP ADD/SUB/MUL/DIV autovec for VLS mode
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating
From: Pan Li
This patch would like to allow the VLS mode autovec for the
floating-point binary operation ADD/SUB/MUL/DIV.
Given below code example:
test (float *out, float *in1, float *in2)
{
for (int i = 0; i < 128; i++)
out[i] = in1[i] + in2[i];
}
Before this patch:
test:
csrr a4,vle
