LGTM. Thanks for supporting it :).
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2024-09-12 11:19
To: gcc-patches
CC: juzhe.zhong; kito.cheng; jeffreyalaw; rdapp.gcc; Pan Li
Subject: [PATCH v1] RISC-V: Implement SAT_ADD for signed integer vector
From: Pan Li
This patch would like to implement
From: Pan Li
This patch would like to implement the ssadd for vector integer. Aka
form 1 of ssadd vector.
Form 1:
#define DEF_VEC_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
void __attribute__((noinline)) \
vec_sat_s_add_##T##_fmt_1 (T *out
