Committed, thanks Juzhe.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 23, 2023 9:44 AM
To: Li, Pan2 ; gcc-patches
Cc: Wang, Yanzhang ; kito.cheng
Subject: Re: RE: [PATCH v1] RISC-V: Bugfix for merging undefined tmp register
in math
OK。 LGTM
OK。 LGTM。
juzhe.zh...@rivai.ai
From: Li, Pan2
Date: 2023-10-23 09:42
To: juzhe.zh...@rivai.ai; gcc-patches
CC: Wang, Yanzhang; kito.cheng
Subject: RE: [PATCH v1] RISC-V: Bugfix for merging undefined tmp register in
math
Yes, it is required by the second cvt. The unmasked elements keep the
Yes, it is required by the second cvt. The unmasked elements keep the original
values.
Pan
From: juzhe.zh...@rivai.ai
Sent: Monday, October 23, 2023 9:35 AM
To: Li, Pan2 ; gcc-patches
Cc: Li, Pan2 ; Wang, Yanzhang ;
kito.cheng
Subject: Re: [PATCH v1] RISC-V: Bugfix for merging undefined tmp
; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Bugfix for merging undefined tmp register in math
From: Pan Li
For math function autovec, there will be one step like
rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode);
The MU will leave
From: Pan Li
For math function autovec, there will be one step like
rtx tmp = gen_reg_rtx (vec_int_mode);
emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode);
The MU will leave the tmp (aka dest register) register unmasked elements
unchanged and it is undefined here. This pat
