.@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang
Subject: Re: [PATCH v1] Mode-Switching: Fix SET_SRC ICE when only one operand
On 8/7/23 07:13, Richard Biener wrote:
> On Mon, Aug 7, 2023 at 2:30 PM Pan Li via Gcc-patches
> wrote:
>>
>> From: Pan Li
>>
>> In s
On 8/7/23 07:13, Richard Biener wrote:
On Mon, Aug 7, 2023 at 2:30 PM Pan Li via Gcc-patches
wrote:
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg
nal Message-
From: Richard Biener
Sent: Monday, August 7, 2023 9:14 PM
To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang,
Yanzhang ; jeffreya...@gmail.com
Subject: Re: [PATCH v1] Mode-Switching: Fix SET_SRC ICE when only one operand
On Mon, Aug 7, 2023
On Mon, Aug 7, 2023 at 2:30 PM Pan Li via Gcc-patches
wrote:
>
> From: Pan Li
>
> In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
> be only 1 operand when SET_SRC in create_pre_exit. For example as below.
>
> (insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
> "gcc/testsuite/gc
From: Pan Li
In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will
be only 1 operand when SET_SRC in create_pre_exit. For example as below.
(insn 13 9 14 2 (clobber (reg/i:TI 10 a0))
"gcc/testsuite/gcc.dg/pr78148.c":24:1 -1
(expr_list:REG_UNUSED (reg/i:TI 10 a0)
(nil)))
