Re: [PATCH V5, 2/2] PR target/105325: Fix memory constraints for power10 fusion.

2023-05-26 Thread Segher Boessenkool
On Wed, May 10, 2023 at 11:40:00AM -0400, Michael Meissner wrote: > This patch applies stricter predicates and constraints for LD and LWA > instructions with power10 fusion. These instructions are DS-form > instructions, > which means that the bottom 2 bits of the address must be 0. The low two

[PATCH V5, 2/2] PR target/105325: Fix memory constraints for power10 fusion.

2023-05-10 Thread Michael Meissner via Gcc-patches
This patch applies stricter predicates and constraints for LD and LWA instructions with power10 fusion. These instructions are DS-form instructions, which means that the bottom 2 bits of the address must be 0. In the past, we did not use the stricter predicates and constraints, and if the user us