Address comments and send V6.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-06-16 18:10
To: juzhe.zh...@rivai.ai; gcc-patches
CC: rdapp.gcc; rguenther; richard.sandiford
Subject: Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs
> <= (operand 2 + opera
> <= (operand 2 + operand 4) are used."
Sorry it's really minor (and my mistake) but it should be < and
not <=, right? Mask index 0 is inactive when the length is 0.
> +Perform a masked store (operand 2 + operand 4)
Even more minor but as mentioned the "of" is still missing ;)
Same with the
Dapp
Date: 2023-06-16 17:21
To: juzhe.zhong; gcc-patches
CC: rdapp.gcc; rguenther; richard.sandiford
Subject: Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs
Hi Juzhe,
> +@cindex @code{len_maskload@var{m}@var{n}} instruction pattern
> +@item @samp{len_maskload@var{m}
Hi Juzhe,
> +@cindex @code{len_maskload@var{m}@var{n}} instruction pattern
> +@item @samp{len_maskload@var{m}@var{n}}
> +Perform a masked load (operand 2 - operand 4) elements from vector memory
> +operand 1 into vector register operand 0, setting the other elements of
> +operand 0 to undefined va
Thanks a lot! I will wait for Richard final approve.
juzhe.zh...@rivai.ai
From: Richard Biener
Date: 2023-06-16 17:04
To: Ju-Zhe Zhong
CC: gcc-patches; richard.sandiford; rdapp.gcc
Subject: Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs
On Thu, 15 Jun 2023,
On Thu, 15 Jun 2023, juzhe.zh...@rivai.ai wrote:
> From: Ju-Zhe Zhong
>
> This patch bootstrap pass on X86, ok for trunk ?
OK with me, please give Richard S. a chance to comment before pushing.
Thanks,
Richard.
> Accoding to comments from Richi, split the first patch to add ifn && optabs
> of
From: Ju-Zhe Zhong
This patch bootstrap pass on X86, ok for trunk ?
Accoding to comments from Richi, split the first patch to add ifn && optabs
of LEN_MASK_{LOAD,STORE} only, we don't apply them into vectorizer in this
patch. And also add BIAS argument for possible s390's future use.
The descri
