Re: [PATCH V4] RISC-V: Prevent speculative vsetvl insn scheduling

On 5/20/25 4:05 PM, Edwin Lu wrote: The instruction scheduler appears to be speculatively hoisting vsetvl insns outside of their basic block without checking for data dependencies. This resulted in a situation where the following occurs vsetvli a5,a1,e32,m1,tu,ma vle32.v v2,

Re: [PATCH V4] RISC-V: Prevent speculative vsetvl insn scheduling

On 5/20/25 4:05 PM, Edwin Lu wrote: The instruction scheduler appears to be speculatively hoisting vsetvl insns outside of their basic block without checking for data dependencies. This resulted in a situation where the following occurs vsetvli a5,a1,e32,m1,tu,ma vle32.v v2,

[PATCH V4] RISC-V: Prevent speculative vsetvl insn scheduling

The instruction scheduler appears to be speculatively hoisting vsetvl insns outside of their basic block without checking for data dependencies. This resulted in a situation where the following occurs vsetvli a5,a1,e32,m1,tu,ma vle32.v v2,0(a0) sub a1,a1,a5 <-- a1 poten