Committed to the trunk, thanks Richard and Juzhe.
1. bootstrap and regression are pass on i386 target (by Pan).
2. no new failed testcases on AArch64 target.
Best,
Lehua
-- Original --
From:
juzhe.zh...@rivai.ai writes:
> From: Ju-Zhe Zhong
>
> Hi, Richard.
>
> RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc)
> There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc)
>
> When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS
>
From: Ju-Zhe Zhong
Hi, Richard.
RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc)
There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc)
When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS
(inserted after RA) ICE:
rvv.c:13:1: intern
