...@sifive.com;
pal...@dabbelt.com; pal...@rivosinc.com; jeffreya...@gmail.com;
rdapp@gmail.com; Li, Pan2
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS
Why didn't you test that??
../../gcc/config/riscv/riscv-vsetvl.cc: In member function '
Why didn't you test that??
../../gcc/config/riscv/riscv-vsetvl.cc: In member function 'bool
pass_vsetvl::global_eliminate_vsetvl_insn(const rtl_ssa::bb_info*) const':
../../gcc/config/riscv/riscv-vsetvl.cc:4354:3: error: 'vsetvl_rinsn' may be
used uninitialized [-Werror=maybe-uninitialized]
435
Jeff Law via Gcc-patches writes:
> On 6/9/23 04:41, juzhe.zh...@rivai.ai wrote:
>> @@ -4342,135 +4510,81 @@ pass_vsetvl::cleanup_insns (void) const
>> }
>> }
>>
>> +/* Return true if the SET result is not used by any instructions. */
>> +static bool
>> +has_no_uses (basic_block cfg_bb,
Ok. Thanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-09 23:09
To: 钟居哲; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS
On 6/9/23 08:58, 钟居哲 wrote:
>>> I'd pr
On 6/9/23 08:58, 钟居哲 wrote:
I'd probably adjust the name as well. There's an important exception to
returning the first vsetvl -- you stop the search if you encounter a
user RVV instruction.
Could you give me a function name of this?
like:
get_first_vsetvl_prior_all_rvv_insns
is it ok? But
But I think the name is too long.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-09 22:33
To: juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS
On 6/9/23 04:41, juzhe
hanks.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2023-06-09 22:33
To: juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS
On 6/9/23 04:41, juzhe.zh...@rivai.ai wrote:
> F
On 6/9/23 04:41, juzhe.zh...@rivai.ai wrote:
From: Juzhe-Zhong
This patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 5 &&
Phase 6
are quite messy and cause some bugs discovered by my downstream
auto-vectorization
test-generator.
Before this patch.
Phase 5 is cleanup_insns
This patch removed 2nd time initialization of RTL_SSA which is the approach we
both hate.
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-06-09 18:45
To: juzhe.zhong
CC: gcc-patches; kito.cheng; palmer; palmer; jeffreyalaw; rdapp.gcc; pan2.li
Subject: Re: [PATCH V2] RISC-V: Rework Phase 5
Thankful you send this before weekend, I could run the fuzzy testing
during this weekend :P
On Fri, Jun 9, 2023 at 6:41 PM wrote:
>
> From: Juzhe-Zhong
>
> This patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 5 &&
> Phase 6
> are quite messy and cause some bugs discovered by my
From: Juzhe-Zhong
This patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 5 &&
Phase 6
are quite messy and cause some bugs discovered by my downstream
auto-vectorization
test-generator.
Before this patch.
Phase 5 is cleanup_insns is the function remove AVL operand dependency fro
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