Re: [PATCH V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns

Hi Robin, There is one issue with this patch and the next few patches, the mask policy for the generated vsetvl should be mu, which is currently done wrong. I'm going to clear the expand_cond_len* functions before sending the next version of these patches. Then these patches can directly use

Re: [PATCH V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns

Hi Lehua, thanks, LGTM. One thing maybe for the next patches: It seems to me that we lump all of the COND_... tests into the cond subdirectory when IMHO they would also fit into the respective directories of their operations (binop, unop etc). Right now we will have a lot of rather unrelated tes

[PATCH V2] RISC-V: Add conditional autovec convert(INT<->INT) patterns

V2 changes: Address comments from Robin. Hi, This patch adds conditional sign/zero extension and truncation autovec patterns by combining convert and vcond_mask patterns. For quad truncation, two vncvt instructions are generated. This patch combine the second vncvt and vmerge to form a masked vn