On Mon, Aug 18, 2014 at 9:48 AM, Yuri Rumyantsev wrote:
> Your patch is not complete since yo missed two another bit
> manipulation instruction - lzcnt and tzcnt which have the same
Are you sure you are looking at the correct patch? The last one
handles all three instructions.
> deficiency. Mor
Uros,
Your patch is not complete since yo missed two another bit
manipulation instruction - lzcnt and tzcnt which have the same
deficiency. Moreover, I don't think that we need to do it for INTEL
target since it is related to SILVERMONT target rather than BIG COREs.
Should I modify your patch or y
On Fri, Aug 15, 2014 at 2:26 PM, Yuri Rumyantsev wrote:
> Is it important to have correct value for length attribute for Big Cores?
> As I new this attribute is used for code layout alignment.
>
> 2014-08-15 15:54 GMT+04:00 Jakub Jelinek :
>> On Fri, Aug 15, 2014 at 03:45:33PM +0400, Yuri Rumyant
Jakub,
Is it important to have correct value for length attribute for Big Cores?
As I new this attribute is used for code layout alignment.
2014-08-15 15:54 GMT+04:00 Jakub Jelinek :
> On Fri, Aug 15, 2014 at 03:45:33PM +0400, Yuri Rumyantsev wrote:
>> gcc/ChangeLog
>> 2014-08-15 Yuri Rumyantsev
On Fri, Aug 15, 2014 at 03:45:33PM +0400, Yuri Rumyantsev wrote:
> gcc/ChangeLog
> 2014-08-15 Yuri Rumyantsev
>
> PR target/62011
> * config/i386/i386-protos.h (ix86_avoid_false_dep_for_bm): New function
> prototype.
> * config/i386/i386.c (ix86_avoid_false_dep_for_bm): New function.
> * confi
I checked that zeroing destination operand for unary bit-manipulation
instruction is helpful for 64- and 32-bit mode only. So the patch was
changed.
Is it OK for trunk?
gcc/ChangeLog
2014-08-15 Yuri Rumyantsev
PR target/62011
* config/i386/i386-protos.h (ix86_avoid_false_dep_for_bm): New func
It does not help Silvermont, i.e. only Haswell and SandyBridge are affected.
I don't use splitter since (1) it deletes zeroing of dest reg; (2)
scheduler can hoist them up . I will try r16/r32 variants and tell you
later.
2014-08-14 19:18 GMT+04:00 H.J. Lu :
> On Thu, Aug 14, 2014 at 4:50 AM, Yuri
On Thu, Aug 14, 2014 at 4:50 AM, Yuri Rumyantsev wrote:
> Hi All,
>
> Here is a fix for PR 62011 - remove false dependency for unary
> bit-manipulation instructions for latest BigCore chips (Sandybridge
> and Haswell) by outputting in assembly file zeroing destination
> register before bmi instruc
On Thu, Aug 14, 2014 at 4:06 PM, Ilya Enkovich wrote:
> 2014-08-14 18:00 GMT+04:00 Alexander Monakov :
>>
>>
>> On Thu, 14 Aug 2014, Yuri Rumyantsev wrote:
>>
>>> Hi All,
>>>
>>> Here is a fix for PR 62011 - remove false dependency for unary
>>> bit-manipulation instructions for latest BigCore chi
For example, for the first loop for attached test-case we do not
prepend xor to popcnt because of using destination register:
.L23:
leal 1(%rdx), %ecx
popcntq (%rbx,%rax,8), %rax
leal 2(%rdx), %r8d
popcntq (%rbx,%rcx,8), %rcx
addq %rax, %rcx
leal 3(%rdx), %esi
xorq %rax, %rax
popcntq (%rbx,%r8,8),
2014-08-14 18:00 GMT+04:00 Alexander Monakov :
>
>
> On Thu, 14 Aug 2014, Yuri Rumyantsev wrote:
>
>> Hi All,
>>
>> Here is a fix for PR 62011 - remove false dependency for unary
>> bit-manipulation instructions for latest BigCore chips (Sandybridge
>> and Haswell) by outputting in assembly file ze
On Thu, 14 Aug 2014, Yuri Rumyantsev wrote:
> Hi All,
>
> Here is a fix for PR 62011 - remove false dependency for unary
> bit-manipulation instructions for latest BigCore chips (Sandybridge
> and Haswell) by outputting in assembly file zeroing destination
> register before bmi instruction. I c
Hi All,
Here is a fix for PR 62011 - remove false dependency for unary
bit-manipulation instructions for latest BigCore chips (Sandybridge
and Haswell) by outputting in assembly file zeroing destination
register before bmi instruction. I checked that performance restored
for popcnt, lzcnt and tzcn
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