On Wed, Feb 07, 2024 at 05:38:46PM +0800, Kewen.Lin wrote:
> >>> -(define_insn_and_split "*movxo"
> >>> +(define_insn_and_split "*movxo_nodm"
> >>>[(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
> >>> (match_operand:XO 1 "input_operand" "ZwO,d,d"))]
> >>> - "TARGET_MMA
> >>> +
on 2024/2/7 08:06, Michael Meissner wrote:
> On Thu, Jan 25, 2024 at 05:28:49PM +0800, Kewen.Lin wrote:
>> Hi Mike,
>>
>> on 2024/1/6 07:38, Michael Meissner wrote:
>>> The MMA subsystem added the notion of accumulator registers as an optional
>>> feature of ISA 3.1 (power10). In ISA 3.1, these ac
On Thu, Jan 25, 2024 at 05:28:49PM +0800, Kewen.Lin wrote:
> Hi Mike,
>
> on 2024/1/6 07:38, Michael Meissner wrote:
> > The MMA subsystem added the notion of accumulator registers as an optional
> > feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped
> > with
> > the traditi
Hi Mike,
on 2024/1/6 07:38, Michael Meissner wrote:
> The MMA subsystem added the notion of accumulator registers as an optional
> feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with
> the traditional floating point registers 0..31, but logically the accumulator
> registe
Ping
| Date: Fri, 5 Jan 2024 18:38:23 -0500
| From: Michael Meissner
| Subject: Repost [PATCH 3/6] PowerPC: Add support for accumulators in DMR
registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2024-January/641963.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with
the traditional floating point registers 0..31, but logically the accumulator
registers were separate from the FPR registers. In ISA 3.1, it was
Ping #2
| Date: Wed, 18 Oct 2023 20:01:54 -0400
| From: Michael Meissner
| Subject: [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633514.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
Ping patch:
| ate: Wed, 18 Oct 2023 20:01:54 -0400
| From: Michael Meissner
| Subject: [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
| Message-ID:
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/633513.html
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts
The MMA subsystem added the notion of accumulator registers as an optional
feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with
the traditional floating point registers 0..31, but logically the accumulator
registers were separate from the FPR registers. In ISA 3.1, it was
Ping patch. We really would like to get these possibly future PowerPC patches
into GCC 13.
| Date: Wed, 9 Nov 2022 21:46:36 -0500
| Subject: [PATCH 3/6] PowerPC: Add support for accumulators in DMR registers.
| Message-ID:
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
The MMA system added the notion of accumulator registers. In power10, these
accumulators overlapped with the FPR registers, but logically the accumulators
were separate from the FPR registers. It is anticipated that in future
systems, we may have a separate dense math unit and the accumulators wi
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