Please find:
https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release
These instructions are from "3.1.26. NDS.FFB" to "3.1.29. NDS.FLMISM"
in AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf.
Thanks.
Jeff Law 於 2025年7月30日 週三 下午11:22寫道：
>
>
>
> On 7/29/25 7:41 PM, KuanLin Chen wro
On 7/29/25 7:41 PM, KuanLin Chen wrote:
+
+;;
+;;
+;;
+;;String Extension
+;;
+;;
+;;
+
+(define_insn "riscv_nds_ffb"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (unspec:GPR [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
+
Jeff Law 於 2025年7月22日 週二 上午6:34寫道：
Hi Jeff,
Thanks your review.
> > +
> > +(define_insn "*nds_branch_imms7"
> > + [(set (pc)
> > + (if_then_else
> > + (match_operator 1 "equality_operator"
> > + [(match_operand:X 2 "register_operand" "r")
> > + (match_operand:X 3 "ad
On 7/11/25 2:57 AM, Kuan-Lin Chen wrote:
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added int
This patch adds support for the XAndesperf ISA extension.
The 32-bit AndeStar V5 extension includes branch instructions,
load effective address instructions, and string processing
instructions for performance improvement.
New INSN patterns are added into the new file andes.md
as a seprated vender e
Hi Kito,
>>* +(define_predicate "extract_loc_imm_si"*
> Rename it to unsigned_5_bit_integer_operand
>>* + (and (match_code "const_int")
*>>* +(match_test "IN_RANGE (INTVAL (op), 0, 31)")))
*>>* +*
>>* +(define_predicate "extract_loc_imm_di"*
> Rename it to unsigned_6_bit_integer_operand
