:06 AM
To: Li Xu ; gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2
Subject: Re: [PATCH 2/2] RISC-V: Add testcases for signed vector SAT_ADD IMM
form 1
On 5/19/25 2:42 AM, Li Xu wrote:
> From: xuli
>
>
On 5/19/25 2:42 AM, Li Xu wrote:
From: xuli
This patch adds testcase for form1, as shown below:
void __attribute__((noinline)) \
vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \
{
From: xuli
This patch adds testcase for form1, as shown below:
void __attribute__((noinline)) \
vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \
{\
unsigned i;
<--- here.
Pan
-Original Message-
From: Li Xu
Sent: Thursday, January 2, 2025 4:04 PM
To: gcc-patches@gcc.gnu.org
Cc: kito.ch...@gmail.com; richard.guent...@gmail.com; tamar.christ...@arm.com;
juzhe.zh...@rivai.ai; Li, Pan2 ; jeffreya...@gmail.com;
rdapp@gmail.com; xuli
Sub
From: xuli
This patch adds testcase for form1, as shown below:
void __attribute__((noinline)) \
vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \
{\
unsigned i;