On 15 September 2017 at 18:01, Kyrill Tkachov
wrote:
> From what I can tell Ramana and Richard preferred to encode this attribute
> as
> a tuning struct property rather than an inline conditional based on
> arm_arch7.
> I agree that if we want to use that information, it should be encoded this
>
On 15/09/17 16:38, Charles Baylis wrote:
On 13 September 2017 at 10:02, Kyrill Tkachov
wrote:
Hi Charles,
On 12/09/17 09:34, charles.bay...@linaro.org wrote:
From: Charles Baylis
Add bus widths. These use the approximation that v7 and later cores have
64bit data bus width, and earlier cor
piler which is sensitive to that difference. It's done this way
because Ramana and Richard wanted it done that way
(https://gcc.gnu.org/ml/gcc-patches/2017-06/msg00652.html).
From b7bec2e4f7ca0335e0e5bd84c297215a3a7fb8c7 Mon Sep 17 00:00:00 2001
From: Charles Baylis
Date: Fri, 8 Sep 2017 12:53
Hi Charlie,
I can't see any use for adding a bus width to tune params. There are many
different buses in a modern CPU, so there is no such thing as a single
"bus width".
What we need is to add separate costs for the different kinds of loads and
stores. The timings for these depend mostly on the m
Hi Charles,
On 12/09/17 09:34, charles.bay...@linaro.org wrote:
From: Charles Baylis
Add bus widths. These use the approximation that v7 and later cores have
64bit data bus width, and earlier cores have 32 bit bus width, with the
exception of v7m.
Given the way this field is used in patch 2
From: Charles Baylis
Add bus widths. These use the approximation that v7 and later cores have
64bit data bus width, and earlier cores have 32 bit bus width, with the
exception of v7m.
Charles Baylis
* config/arm/arm-protos.h (struct tune_params): New field
bus_width.
