On Thu, Feb 21, 2019 at 10:31 AM Thiago Macieira
wrote:
>
> On Thursday, 30 August 2018 09:00:10 PST H.J. Lu wrote:
> > On Wed, Aug 29, 2018 at 11:56 PM, Uros Bizjak wrote:
> > >> gcc/config/i386/i386.c | 6 +++---
> > >> 1 file changed, 3 insertions(+), 3 deletions(-)
> > >>
> > >> diff --git a
On Thursday, 30 August 2018 09:00:10 PST H.J. Lu wrote:
> On Wed, Aug 29, 2018 at 11:56 PM, Uros Bizjak wrote:
> >> gcc/config/i386/i386.c | 6 +++---
> >> 1 file changed, 3 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> >> index c437c18a29
On Wed, Aug 29, 2018 at 11:56 PM, Uros Bizjak wrote:
> On Thu, Aug 30, 2018 at 7:14 AM, Thiago Macieira
> wrote:
>> The instruction set first appeared with Westmere, but not all processors
>> in that and the next few generations have the instructions. According to
>> Wikipedia[1], the first gener
On Thu, Aug 30, 2018 at 7:14 AM, Thiago Macieira
wrote:
> The instruction set first appeared with Westmere, but not all processors
> in that and the next few generations have the instructions. According to
> Wikipedia[1], the first generation in which all SKUs have AES
> instructions are Skylake a
The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Ca
