Spencer Abson writes:
> On Thu, Jun 05, 2025 at 06:11:44PM +0100, Richard Sandiford wrote:
>> > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_3.c
>> > b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cvtf_3.c
>> > new file mode 100644
>> > index 000..964264c4114
>> > ---
On Thu, Jun 05, 2025 at 06:11:44PM +0100, Richard Sandiford wrote:
> Spencer Abson writes:
> > @@ -9487,21 +9489,39 @@
> > ;; - FCVTZU
> > ;;
> > -
> >
> > -;; Unpredicated conversion of floats to integers of the same siz
Richard Sandiford writes:
>> ;; Predicated float-to-integer conversion, either to the same width or
>> wider.
>> (define_insn
>> "@aarch64_sve__nontrunc"
>>[(set (match_operand:SVE_FULL_HSDI 0 "register_operand")
>> @@ -9517,18 +9537,34 @@
>>}
>> )
>>
>> +;; As above, for pairs used
Spencer Abson writes:
> @@ -9487,21 +9489,39 @@
> ;; - FCVTZU
> ;; -
>
> -;; Unpredicated conversion of floats to integers of the same size (HF to HI,
> -;; SF to SI or DF to DI).
> -(define_expand "2"
> - [(set (match_op
Thanks, Alfie. I agree that having a table with just one entry looks a
little odd, but the rest of the file follows this pattern. For example:
;; -
;; [FP] Absolute difference
;;
On 02/06/2025 11:06, Spencer Abson wrote:
This patch introduces expanders for FP<-FP conversions that levarage
partial vector modes. We also extend the INT<-FP and FP<-INT conversions
using the same approach.
The ACLE enables vectorized conversions like the following:
fcvt z0.h, p7/m, z1.s
Mo
This patch introduces expanders for FP<-FP conversions that levarage
partial vector modes. We also extend the INT<-FP and FP<-INT conversions
using the same approach.
The ACLE enables vectorized conversions like the following:
fcvt z0.h, p7/m, z1.s
Modelling the source vector as VNx4SF:
... |
