Re: PING^1 [PATCH] x86: Add -mmove-max=bits and -mstore-max=bits

2021-12-03 Thread H.J. Lu via Gcc-patches
On Fri, Dec 3, 2021 at 8:55 AM Uros Bizjak wrote: > > On Fri, Dec 3, 2021 at 2:24 PM H.J. Lu wrote: > > > > On Thu, Nov 25, 2021 at 2:47 PM H.J. Lu wrote: > > > > > > Add -mmove-max=bits and -mstore-max=bits to enable 256-bit/512-bit move > > > and store, independent of -mprefer-vector-width=bit

Re: PING^1 [PATCH] x86: Add -mmove-max=bits and -mstore-max=bits

2021-12-03 Thread Uros Bizjak via Gcc-patches
On Fri, Dec 3, 2021 at 2:24 PM H.J. Lu wrote: > > On Thu, Nov 25, 2021 at 2:47 PM H.J. Lu wrote: > > > > Add -mmove-max=bits and -mstore-max=bits to enable 256-bit/512-bit move > > and store, independent of -mprefer-vector-width=bits: > > > > 1. Add X86_TUNE_AVX512_MOVE_BY_PIECES and X86_TUNE_AVX

PING^1 [PATCH] x86: Add -mmove-max=bits and -mstore-max=bits

2021-12-03 Thread H.J. Lu via Gcc-patches
On Thu, Nov 25, 2021 at 2:47 PM H.J. Lu wrote: > > Add -mmove-max=bits and -mstore-max=bits to enable 256-bit/512-bit move > and store, independent of -mprefer-vector-width=bits: > > 1. Add X86_TUNE_AVX512_MOVE_BY_PIECES and X86_TUNE_AVX512_STORE_BY_PIECES > which are enabled for Intel Sapphire Ra

[PATCH] x86: Add -mmove-max=bits and -mstore-max=bits

2021-11-25 Thread H.J. Lu via Gcc-patches
Add -mmove-max=bits and -mstore-max=bits to enable 256-bit/512-bit move and store, independent of -mprefer-vector-width=bits: 1. Add X86_TUNE_AVX512_MOVE_BY_PIECES and X86_TUNE_AVX512_STORE_BY_PIECES which are enabled for Intel Sapphire Rapids processor. 2. Add -mmove-max=bits to set the maximum n