> As a general comment it would be nicer if the cost metric itself would focus
> on size costs when optimizing for size and speed costs when optimizing for
> speed so that individual STV opportunities can be enabled/disabled based
> on it.
Agreed. I think the cost computation should consider insn
On Thu, Apr 14, 2022 at 10:31 AM Hongyu Wang wrote:
>
> > >virtual bool gate (function *)
> >
> > please name the parameter ...
> >
> > > {
> > >return ((!timode_p || TARGET_64BIT)
> > > - && TARGET_STV && TARGET_SSE2 && optimize > 1);
> > > + && TARGET_STV && TARGET_S
> >virtual bool gate (function *)
>
> please name the parameter ...
>
> > {
> >return ((!timode_p || TARGET_64BIT)
> > - && TARGET_STV && TARGET_SSE2 && optimize > 1);
> > + && TARGET_STV && TARGET_SSE2 && optimize > 1
> > + && optimize_function_for_speed_p (cfun)
On Thu, Apr 14, 2022 at 9:55 AM Hongyu Wang wrote:
>
> >
> > optimize_function_for_speed ()?
> >
>
> Yes, updated patch with optimize_function_for_speed_p()
>
> gcc/ChangeLog:
>
> PR target/105034
> * config/i386/i386-features.cc (pass_stv::gate()): Add
> optimize_function_for_speed_p ().
>
> gc
>
> optimize_function_for_speed ()?
>
Yes, updated patch with optimize_function_for_speed_p()
gcc/ChangeLog:
PR target/105034
* config/i386/i386-features.cc (pass_stv::gate()): Add
optimize_function_for_speed_p ().
gcc/testsuite/ChangeLog:
PR target/105034
* gcc.target/i386/pr105034.c: New t
On Thu, Apr 14, 2022 at 3:18 AM Hongyu Wang via Gcc-patches
wrote:
>
> Hi,
>
> From -Os point of view, stv converts scalar register to vector mode
> which introduces extra reg conversion and increase instruction size.
> Disabling stv under optimize_size would avoid such code size increment
> and n
Hi,
>From -Os point of view, stv converts scalar register to vector mode
which introduces extra reg conversion and increase instruction size.
Disabling stv under optimize_size would avoid such code size increment
and no need to touch ix86_size_cost that has not been tuned for long
time.
Bootstrap
