Soumya AR writes:
>> On 1 Oct 2024, at 6:17 PM, Richard Sandiford
>> wrote:
>>
>> External email: Use caution opening links or attachments
>>
>>
>> Soumya AR writes:
>>> Currently, we vectorize CTZ for SVE by using the following operation:
>>> .CTZ (X) = (PREC - 1) - .CLZ (X & -X)
>>>
>>> Inste
> On 1 Oct 2024, at 6:17 PM, Richard Sandiford
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> Soumya AR writes:
>> Currently, we vectorize CTZ for SVE by using the following operation:
>> .CTZ (X) = (PREC - 1) - .CLZ (X & -X)
>>
>> Instead, this patch expands CTZ t
Soumya AR writes:
> Currently, we vectorize CTZ for SVE by using the following operation:
> .CTZ (X) = (PREC - 1) - .CLZ (X & -X)
>
> Instead, this patch expands CTZ to RBIT + CLZ for SVE, as suggested in
> PR109498.
>
> The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression
Reworked the patch to substitute immediate register values in the test case with
regular expressions. Apologies for the oversight.
Thanks,
Soumya
> On 24 Sep 2024, at 8:53 AM, Soumya AR wrote:
>
> Currently, we vectorize CTZ for SVE by using the following operation:
> .CTZ (X) = (PREC - 1) - .
Currently, we vectorize CTZ for SVE by using the following operation:
.CTZ (X) = (PREC - 1) - .CLZ (X & -X)
Instead, this patch expands CTZ to RBIT + CLZ for SVE, as suggested in PR109498.
The patch was bootstrapped and regtested on aarch64-linux-gnu, no regression.
OK for mainline?
Signed-off-b
