On Tue, Apr 19, 2016 at 5:36 PM, H.J. Lu wrote:
> On Tue, Apr 19, 2016 at 8:27 AM, Uros Bizjak wrote:
>> On Tue, Apr 19, 2016 at 5:18 PM, H.J. Lu wrote:
>>> On Tue, Apr 19, 2016 at 8:08 AM, Uros Bizjak wrote:
On Tue, Apr 19, 2016 at 4:49 PM, H.J. Lu wrote:
>
> From INSTRUCTION EXC
On Tue, Apr 19, 2016 at 8:27 AM, Uros Bizjak wrote:
> On Tue, Apr 19, 2016 at 5:18 PM, H.J. Lu wrote:
>> On Tue, Apr 19, 2016 at 8:08 AM, Uros Bizjak wrote:
>>> On Tue, Apr 19, 2016 at 4:49 PM, H.J. Lu wrote:
From INSTRUCTION EXCEPTION SPECIFICATION section in Intel software
deve
On Tue, Apr 19, 2016 at 5:18 PM, H.J. Lu wrote:
> On Tue, Apr 19, 2016 at 8:08 AM, Uros Bizjak wrote:
>> On Tue, Apr 19, 2016 at 4:49 PM, H.J. Lu wrote:
>>>
>>> From INSTRUCTION EXCEPTION SPECIFICATION section in Intel software
>>> developer manual volume 2, only legacy SSE instructions with mem
On Tue, Apr 19, 2016 at 8:08 AM, Uros Bizjak wrote:
> On Tue, Apr 19, 2016 at 4:49 PM, H.J. Lu wrote:
>>
>> From INSTRUCTION EXCEPTION SPECIFICATION section in Intel software
>> developer manual volume 2, only legacy SSE instructions with memory
>> operand not 16-byte aligned get General Protecti
On Tue, Apr 19, 2016 at 4:49 PM, H.J. Lu wrote:
>
> From INSTRUCTION EXCEPTION SPECIFICATION section in Intel software
> developer manual volume 2, only legacy SSE instructions with memory
> operand not 16-byte aligned get General Protection fault. There is
> no need to check 1, 2, 4, 8 byte alig
>From INSTRUCTION EXCEPTION SPECIFICATION section in Intel software
developer manual volume 2, only legacy SSE instructions with memory
operand not 16-byte aligned get General Protection fault. There is
no need to check 1, 2, 4, 8 byte alignments. Since x86 backend has
accurate constraints and p
