Re: [PATCH] RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV

On Tue, Nov 7, 2023 at 9:07 AM Juzhe-Zhong wrote: > > Previously, in this patch: > https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635392.html > I use vect64 && vect128 to represent both RVV and AMDGCN. However, it caused > additional FAIL on ARM SVE. > I don't know why ARM SVE vect64 is

[PATCH] RISC-V regression test: Fix FAIL bb-slp-cond-1.c for RVV

Previously, in this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-November/635392.html I use vect64 && vect128 to represent both RVV and AMDGCN. However, it caused additional FAIL on ARM SVE. I don't know why ARM SVE vect64 is set as true since their AdvSIMD is 128bit vector and they don