On Tue, 10 Oct 2023, Juzhe-Zhong wrote:
> Here is the reference comparing dump IR between ARM SVE and RVV.
>
> https://godbolt.org/z/zqess8Gss
>
> We can see RVV has one more dump IR:
> optimized: basic block part vectorized using 128 byte vectors
> since RVV has 1024 bit vectors.
>
> The codeg
Great ! I am gonna wait for Richi's approval.
juzhe.zh...@rivai.ai
From: Andrew Stubbs
Date: 2023-10-10 17:40
To: Juzhe-Zhong; gcc-patches@gcc.gnu.org
CC: rguent...@suse.de; jeffreya...@gmail.com
Subject: Re: [PATCH] RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV
On 10/10/2023
On 10/10/2023 02:39, Juzhe-Zhong wrote:
Here is the reference comparing dump IR between ARM SVE and RVV.
https://godbolt.org/z/zqess8Gss
We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.
The codegen is reasonable
Here is the reference comparing dump IR between ARM SVE and RVV.
https://godbolt.org/z/zqess8Gss
We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.
The codegen is reasonable good.
However, I saw GCN also has 1024 bi
