On 2/13/25 20:46, Jeff Law wrote:
>> BTW what exactly is speculative scheduling ? As in what is it actually
>> trying to
>> schedule ahead ?
> In simplest terms assume we have this kind of graph
>
> 0
> / \
>1-->2
>
>
> The scheduler knows how to build scheduling regions, essentially
On 2/14/25 04:58, Jeff Law wrote:
> I'd guess it more work than it'd be worth. We're just not seeing
> vsetvls being all that problematical on our design. I do see a lot of
> seemingly gratutious changes in the vector config, but when we make
> changes to fix that we generally end up with wors
On 2/13/25 11:13 AM, Palmer Dabbelt wrote:
FWIW, that's what tripped up my "maybe there's a functional bug here"
thought. It looks like the scheduling is seeing
bne t0, x0, end
vsetvli t1, t2, ...
vsetvli x0, t2, ...
...
end:
vsetvli x0, t2, ...
and thinking it's s
On 2/13/25 11:57 AM, Robin Dapp wrote:
I did try adding some additional logic to adjust the way vsetvl fusion
occurs across basic blocks in these scenarios i.e. performing the
fusion in the opposite manner (breaking lcm guarantees); however, from
my testing, fusing two vsetvls didn't actually
> I did try adding some additional logic to adjust the way vsetvl fusion
> occurs across basic blocks in these scenarios i.e. performing the
> fusion in the opposite manner (breaking lcm guarantees); however, from
> my testing, fusing two vsetvls didn't actually remove the fused
> expression f
On 2/13/2025 4:12 AM, Vineet Gupta wrote:
On 2/13/25 14:17, Robin Dapp wrote:
Other thoughts?
The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
we can't/don't model in the pipeline, but I have no idea how to model
the VL=0 case there.
Maybe so, but what Edwin is doing
On Thu, 13 Feb 2025 06:46:10 PST (-0800), jeffreya...@gmail.com wrote:
On 2/13/25 1:47 AM, Robin Dapp wrote:
Other thoughts?
The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
we can't/don't model in the pipeline, but I have no idea how to model
the VL=0 case there.
Ma
On Thu, 13 Feb 2025 07:38:13 PST (-0800), jeffreya...@gmail.com wrote:
On 2/13/25 8:19 AM, Robin Dapp wrote:
The vsevl pass is LCM based. So it's not allowed to add a vsetvl on a
path that didn't have a vsetvl before. Consider this simple graph.
0
/ \
2-->3
If we have need f
On 2/13/25 8:19 AM, Robin Dapp wrote:
The vsevl pass is LCM based. So it's not allowed to add a vsetvl on a
path that didn't have a vsetvl before. Consider this simple graph.
0
/ \
2-->3
If we have need for a vsetvl in bb2, but not bb0 or bb3, then the vsetvl
will land in bb
> Yeah, I remember the same issue with the rounding-mode setter placement.
>
> Wouldn't that be fixable by requiring a dummy/wildcard/dontcare vsetvl in bb3
> (or any other block that doesn't require one)? Such a dummy vsetvl would be
> fusible with every other vsetvl. If there are dummy vsetvls
> The vsevl pass is LCM based. So it's not allowed to add a vsetvl on a
> path that didn't have a vsetvl before. Consider this simple graph.
>
> 0
> / \
>2-->3
>
> If we have need for a vsetvl in bb2, but not bb0 or bb3, then the vsetvl
> will land in bb4. bb0 is not a valid inserti
On 2/13/25 5:12 AM, Vineet Gupta wrote:
On 2/13/25 14:17, Robin Dapp wrote:
Other thoughts?
The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
we can't/don't model in the pipeline, but I have no idea how to model
the VL=0 case there.
Maybe so, but what Edwin is doing l
On 2/13/25 1:47 AM, Robin Dapp wrote:
Other thoughts?
The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
we can't/don't model in the pipeline, but I have no idea how to model
the VL=0 case there.
Maybe so, but what Edwin is doing looks sensible enough. It wouldn't be
On 2/13/25 14:17, Robin Dapp wrote:
Other thoughts?
>>> The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
>>> we can't/don't model in the pipeline, but I have no idea how to model
>>> the VL=0 case there.
>> Maybe so, but what Edwin is doing looks sensible enough. It
>>> Other thoughts?
>>
>> The docs seem to hint TARGET_SCHED_CAN_SPECULATE_INSN is meant for stuff
>> we can't/don't model in the pipeline, but I have no idea how to model
>> the VL=0 case there.
> Maybe so, but what Edwin is doing looks sensible enough. It wouldn't be
> the first time a hook
On 2/12/25 9:23 PM, Palmer Dabbelt wrote:
PR/117974
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_can_speculate_insn):
(TARGET_SCHED_CAN_SPECULATE_INSN): Implement.
Correct me if I'm wrong, there's not anything inherently wrong with the
speculation from a correctness sta
On Wed, 12 Feb 2025 16:47:07 PST (-0800), jeffreya...@gmail.com wrote:
On 2/12/25 4:27 PM, Edwin Lu wrote:
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the fol
in scheduler.
juzhe.zh...@rivai.ai
From: Jeff Law
Date: 2025-02-13 11:33
To: 钟居哲; ewlu; gcc-patches
CC: gnu-toolchain; vineetg
Subject: Re: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
On 2/12/25 6:44 PM, 钟居哲 wrote:
> VSETVL PASS is supposed to insert "vsetvli&
On 2/12/25 6:44 PM, 钟居哲 wrote:
VSETVL PASS is supposed to insert "vsetvli" into optimal place so
"vsetvli" inserted by VSETVL PASS shouldn't involved into instruction
scheduling.
vsetvl pass inserts based on needs of vector instructions. The
scheduler will move code to try and minimize the
zhong
Subject: Re: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
On 2/12/25 4:27 PM, Edwin Lu wrote:
> The instruction scheduler appears to be speculatively hoisting vsetvl
> insns outside of their basic block without checking for data
> dependencies. This resulted in a si
On 2/12/25 4:27 PM, Edwin Lu wrote:
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,
<mailto:juzhe.zh...@rivai.ai>; Edwin Lu <mailto:e...@rivosinc.com>
*Subject:* [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
depende
Could you add PR117974 testcase ?
juzhe.zh...@rivai.ai
From: Edwin Lu
Date: 2025-02-13 07:27
To: gcc-patches
CC: gnu-toolchain; vineetg; juzhe.zhong; Edwin Lu
Subject: [PATCH] RISC-V: Prevent speculative vsetvl insn scheduling
The instruction scheduler appears to be speculatively hoisting
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5 <-- a1 poten
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