On Mon, 21 Nov 2022 at 04:11, Kito Cheng wrote:
>
> > @@ -464,6 +464,60 @@
> >[(set_attr "type" "arith")
> > (set_attr "mode" "DI")])
> >
> > +(define_expand "add3"
> > + [(set (match_operand:GPR 0 "register_operand" "=r,r")
> > + (plus:GPR (match_operand:GPR 1 "regis
> @@ -464,6 +464,60 @@
>[(set_attr "type" "arith")
> (set_attr "mode" "DI")])
>
> +(define_expand "add3"
> + [(set (match_operand:GPR 0 "register_operand" "=r,r")
> + (plus:GPR (match_operand:GPR 1 "register_operand" " r,r")
> + (match_operand:GPR
On 11/18/22 14:26, Philipp Tomsich wrote:
On Fri, 18 Nov 2022 at 22:13, Jeff Law wrote:
On 11/9/22 16:07, Philipp Tomsich wrote:
Handling the register-const_int addition has very quickly escalated to
creating a full sign-extended 32bit constant and performing a
register-register for RISC-V
On Fri, 18 Nov 2022 at 22:13, Jeff Law wrote:
>
>
> On 11/9/22 16:07, Philipp Tomsich wrote:
> > Handling the register-const_int addition has very quickly escalated to
> > creating a full sign-extended 32bit constant and performing a
> > register-register for RISC-V in GCC so far, resulting in seq
On 11/9/22 16:07, Philipp Tomsich wrote:
Handling the register-const_int addition has very quickly escalated to
creating a full sign-extended 32bit constant and performing a
register-register for RISC-V in GCC so far, resulting in sequences like
(for the case of "a + 2048"):
li a5,
Handling the register-const_int addition has very quickly escalated to
creating a full sign-extended 32bit constant and performing a
register-register for RISC-V in GCC so far, resulting in sequences like
(for the case of "a + 2048"):
li a5,4096
addia5,a5,-2048
add
