Re: [PATCH] RISC-V: Libitm add RISC-V support.

I'm surprised by the hard-coded 128-byte cache line size. If we need to hard-code a value, it should be 64 (in accordance with the RVA profiles, see https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc), but ideally this would be queried dynamically. On Thu, Oct 27, 2022 at 3:51 AM Xi

[PATCH] RISC-V: Libitm add RISC-V support.

libitm/ChangeLog: * configure.tgt: Add riscv support. * config/riscv/asm.h: New file. * config/riscv/sjlj.S: New file. * config/riscv/target.h: New file. --- libitm/config/riscv/asm.h| 52 + libitm/config/riscv/sjlj.S | 144 ++