RE: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store

Cc: Kito.cheng ; Wang, Yanzhang Subject: RE: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store Thanks Juzhe, make sense, let me update it soon. Pan From: juzhe.zh...@rivai.ai Sent: Thursday, May 4, 2023 4:40 PM To: Li, Pan2 ; gcc-patches Cc: Kito.cheng ; Li, Pan2 ; Wang

RE: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store

Thanks Juzhe, make sense, let me update it soon. Pan From: juzhe.zh...@rivai.ai Sent: Thursday, May 4, 2023 4:40 PM To: Li, Pan2 ; gcc-patches Cc: Kito.cheng ; Li, Pan2 ; Wang, Yanzhang Subject: Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store vluxei32.v v1,(0

Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store

ect: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store From: Pan Li This patch try to legitimise the const0_rtx (aka zero register) as the base register for the RVV indexed load/store instructions by allowing the const as the operand of the indexed RTL pattern. Then the underly

[PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed load/store

From: Pan Li This patch try to legitimise the const0_rtx (aka zero register) as the base register for the RVV indexed load/store instructions by allowing the const as the operand of the indexed RTL pattern. Then the underlying combine pass will try to perform the const propagation. For example: