cc Robin an Ju-Zhe
On Tue, Feb 4, 2025 at 3:16 PM Monk Chiang wrote:
>
> According to Section 3.4.2, Vector Register Grouping, in the RISC-V
> Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN
> ---
> gcc/config/riscv/riscv-v.cc | 8 +-
> gcc/config/riscv/riscv-vect
According to Section 3.4.2, Vector Register Grouping, in the RISC-V
Vector Specification, the rule for LMUL is LMUL >= SEW/ELEN
---
gcc/config/riscv/riscv-v.cc | 8 +-
gcc/config/riscv/riscv-vector-switch.def | 84 ++---
.../gcc.target/riscv/rvv/autovec/pr111391-2
