Re: [PATCH] RISC-V: Add zero_extract support for rv64gc

2024-05-08 Thread Christoph Müllner
On Mon, May 6, 2024 at 11:43 PM Vineet Gupta wrote: > > > > On 5/6/24 13:40, Christoph Müllner wrote: > > The combiner attempts to optimize a zero-extension of a logical right shift > > using zero_extract. We already utilize this optimization for those cases > > that result in a single instruction

Re: [PATCH] RISC-V: Add zero_extract support for rv64gc

2024-05-08 Thread Christoph Müllner
On Mon, May 6, 2024 at 11:24 PM Jeff Law wrote: > > > > On 5/6/24 2:40 PM, Christoph Müllner wrote: > > The combiner attempts to optimize a zero-extension of a logical right shift > > using zero_extract. We already utilize this optimization for those cases > > that result in a single instructions.

Re: [PATCH] RISC-V: Add zero_extract support for rv64gc

2024-05-06 Thread Jeff Law
On 5/6/24 3:42 PM, Vineet Gupta wrote: On 5/6/24 13:40, Christoph Müllner wrote: The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_s

Re: [PATCH] RISC-V: Add zero_extract support for rv64gc

2024-05-06 Thread Vineet Gupta
On 5/6/24 13:40, Christoph Müllner wrote: > The combiner attempts to optimize a zero-extension of a logical right shift > using zero_extract. We already utilize this optimization for those cases > that result in a single instructions. Let's add a insn_and_split > pattern that also matches the g

Re: [PATCH] RISC-V: Add zero_extract support for rv64gc

2024-05-06 Thread Jeff Law
On 5/6/24 2:40 PM, Christoph Müllner wrote: The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_split pattern that also matches the gener

[PATCH] RISC-V: Add zero_extract support for rv64gc

2024-05-06 Thread Christoph Müllner
The combiner attempts to optimize a zero-extension of a logical right shift using zero_extract. We already utilize this optimization for those cases that result in a single instructions. Let's add a insn_and_split pattern that also matches the generic case, where we can emit an optimized sequence