Hi Paul-Antoine,
overall the patch looks reasonable to me now, provided the fr2vr followup.
BTW it's the late-combine pass that performs the optimization, not the combine
pass. You might still want to fix this in the commit message.
Please CC patchworks...@rivosinc.com for the next version
Hi Robin,
On 30/05/2025 10:18, Robin Dapp wrote:
BTW it's the late-combine pass that performs the optimization, not the
combine pass. You might still want to fix this in the commit message.
I updated the commit message.
Actually, it depends whether or not the vec_duplicate is hoisted to the
Hi Paul-Antoine,
Please find attached a revised version of the patch.
Compared to the previous iteration, I have:
* Rebased on top of Pan's work;
* Updated the cost model;
* Added a second pattern to handle the case where PLUS_MINUS operands
are swapped;
* Added compile and run tests.
I boot
On 07/05/2025 12:29, Robin Dapp wrote:
Yes, we need it in order to be able to test both paths, i.e. combining
and not combining. Also make sure to test with multiple types and
situations as in Pan's patch.
Please find attached a revised version of the patch.
Compared to the previous iteratio
Thanks Jeff. I will rebase and update my patch. One question though, I
noticed that Pan's patch introduced a command-line parameter to tweak the
GR2VR cost; do we need something equivalent for FR2VR?
Yes, we need it in order to be able to test both paths, i.e. combining and not
combining. Als
On 06/05/2025 15:06, Jeff Law wrote:
diff --git gcc/config/riscv/riscv.cc gcc/config/riscv/riscv.cc
index 38f3ae7cd84..0f0cf04bdd9 100644
--- gcc/config/riscv/riscv.cc
+++ gcc/config/riscv/riscv.cc
@@ -3864,6 +3864,18 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
outer_code, int opno ATTRIBU
On 4/16/25 8:32 AM, Paul-Antoine Arras wrote:
Please find attached an updated patch with an additional cost model. By
default, an instruction is 4 and the penalty for moving data from
floating-point to vector register is 2; thus, vfmadd.vf costs 6, which
still makes it cheaper than vec_du
Hi Jeff, Robin,
Thanks for your comments.
On 30/03/2025 01:30, Jeff Law wrote:
On 3/27/25 1:39 PM, Robin Dapp wrote:
Hi Paul-Antoine,
This pattern enables the combine pass to merge a vec_duplicate into a
plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions,
So may be the way to go is add a field to the uarch tuning structure
indicating the additional cost (if any) of a register file crossing vector op
of this nature. Then query that in riscv_rtx_costs or whatever our rtx_cost
function is named.
Default that additional cost to zero initially. Th
in and Jeff, I will re-send the patch of vadd.vv/vx after stage
1 open, and then all other
similar cases.
Pan
-Original Message-
From: Jeff Law
Sent: Sunday, March 30, 2025 8:31 AM
To: Robin Dapp ; Paul-Antoine Arras ;
gcc-patches@gcc.gnu.org; Li, Pan2
Subject: Re: [PATCH] RISC-V:
On 3/27/25 1:39 PM, Robin Dapp wrote:
Hi Paul-Antoine,
This pattern enables the combine pass to merge a vec_duplicate into a
plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v6,fa0
vfmadd.vv v9,v6,v7
After, we get only o
Hi Paul-Antoine,
This pattern enables the combine pass to merge a vec_duplicate into a plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.fv6,fa0
vfmadd.vv v9,v6,v7
After, we get only one:
vfmadd.vf v9,fa0,v7
On SPEC201
This pattern enables the combine pass to merge a vec_duplicate into a plus-mult
or minus-mult RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.fv6,fa0
vfmadd.vv v9,v6,v7
After, we get only one:
vfmadd.vf v9,fa0,v7
On SPEC2017's 503.bwaves_r, de
13 matches
Mail list logo
