Re: [PATCH] RISC-V: Add new operand constraint: cR

Committed :) On Sat, May 17, 2025 at 9:36 PM Jeff Law wrote: > > > > On 5/14/25 9:20 PM, Kito Cheng wrote: > > This commit introduces a new operand constraint `cR` for the RISC-V > > architecture, which allows the use of an even-odd RVC general purpose > > register > > (x8-x15) in inline asm. >

Re: [PATCH] RISC-V: Add new operand constraint: cR

On 5/14/25 9:20 PM, Kito Cheng wrote: This commit introduces a new operand constraint `cR` for the RISC-V architecture, which allows the use of an even-odd RVC general purpose register (x8-x15) in inline asm. Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102 gcc/ChangeLog:

[PATCH] RISC-V: Add new operand constraint: cR

This commit introduces a new operand constraint `cR` for the RISC-V architecture, which allows the use of an even-odd RVC general purpose register (x8-x15) in inline asm. Ref: https://github.com/riscv-non-isa/riscv-c-api-doc/pull/102 gcc/ChangeLog: * config/riscv/constraints.md (cR): New