Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Jeff Law
On 3/25/24 2:57 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 13:49:18 PDT (-0700), jeffreya...@gmail.com wrote: On 3/25/24 2:31 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote: I'd doubt it's worth the complexity.  Picking some reasonable value gets

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Palmer Dabbelt
On Mon, 25 Mar 2024 13:49:18 PDT (-0700), jeffreya...@gmail.com wrote: On 3/25/24 2:31 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote: I'd doubt it's worth the complexity.  Picking some reasonable value gets you the vast majority of the benefit.   Somethi

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Jeff Law
On 3/25/24 2:31 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote: I'd doubt it's worth the complexity.  Picking some reasonable value gets you the vast majority of the benefit.   Something like COSTS_N_INSNS(6) is enough to get CSE to trigger.  So what's le

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Palmer Dabbelt
On Mon, 25 Mar 2024 13:27:34 PDT (-0700), Jeff Law wrote: On 3/25/24 2:13 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote: On 3/25/24 1:48 PM, Xi Ruoyao wrote: On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: +/* Costs to use when optimizing for xiangs

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Jeff Law
On 3/25/24 2:13 PM, Palmer Dabbelt wrote: On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote: On 3/25/24 1:48 PM, Xi Ruoyao wrote: On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: +/* Costs to use when optimizing for xiangshan nanhu.  */ +static const struct riscv_tune_param xiang

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Palmer Dabbelt
On Mon, 25 Mar 2024 12:59:14 PDT (-0700), Jeff Law wrote: On 3/25/24 1:48 PM, Xi Ruoyao wrote: On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: +/* Costs to use when optimizing for xiangshan nanhu.  */ +static const struct riscv_tune_param xiangshan_nanhu_tune_info = { +  {COSTS_N_INSNS (3)

Re: TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Jeff Law
On 3/25/24 1:48 PM, Xi Ruoyao wrote: On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: +/* Costs to use when optimizing for xiangshan nanhu.  */ +static const struct riscv_tune_param xiangshan_nanhu_tune_info = { +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */ +  {COSTS_N_INSNS

TARGET_RTX_COSTS and pipeline latency vs. variable-latency instructions (was Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.)

2024-03-25 Thread Xi Ruoyao
On Mon, 2024-03-18 at 20:54 -0600, Jeff Law wrote: > > +/* Costs to use when optimizing for xiangshan nanhu.  */ > > +static const struct riscv_tune_param xiangshan_nanhu_tune_info = { > > +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp_add */ > > +  {COSTS_N_INSNS (3), COSTS_N_INSNS (3)}, /* fp

Re: Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

2024-03-19 Thread jiawei
as.ac.cn > 主题: Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture. > > > > On 2/27/24 1:52 AM, Jiawei wrote: > > From: Chen Jiawei > > > > Co-Authored by: Lin Jiawei > > > > This patch add XiangShan Nanhu cpu microarchitecture, > > N

Re: [PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

2024-03-18 Thread Jeff Law
On 2/27/24 1:52 AM, Jiawei wrote: From: Chen Jiawei Co-Authored by: Lin Jiawei This patch add XiangShan Nanhu cpu microarchitecture, Nanhu is a 6-issue, superscalar, out-of-order processor. More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch gcc/ChangeLog: *

[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.

2024-02-27 Thread Jiawei
From: Chen Jiawei Co-Authored by: Lin Jiawei This patch add XiangShan Nanhu cpu microarchitecture, Nanhu is a 6-issue, superscalar, out-of-order processor. More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUN