Re: [PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads

2017-10-25 Thread Palmer Dabbelt
Committed. On Tue, 24 Oct 2017 10:55:46 PDT (-0700), Palmer Dabbelt wrote: > Loads on RISC-V are sign-extending by default, but we weren't telling > GCC this in our PIC load patterns. This corrects the problem, and adds > a zero-extending pattern as well. > > gcc/ChangeLog > > 2017-10-24 Palmer

[PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads

2017-10-24 Thread Palmer Dabbelt
Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-10-24 Palmer Dabbelt * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. * config/ri

[PATCH] RISC-V: Add Sign/Zero extend patterns for PIC loads

2017-05-09 Thread Palmer Dabbelt
Loads on RISC-V are sign-extending by default, but we weren't telling GCC this in our PIC load patterns. This corrects the problem, and adds a zero-extending pattern as well. gcc/ChangeLog 2017-05-09 Palmer Dabbelt * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define. * config/ri