On Wed, Aug 18, 2021 at 3:54 AM Jojo R wrote:
>
>
> — Jojo
> 在 2021年8月16日 +0800 PM3:15,Richard Biener ,写道:
>
> On Fri, Aug 13, 2021 at 3:59 AM Jojo R wrote:
>
>
>
> — Jojo
> 在 2021年8月11日 +0800 PM6:44,Richard Biener ,写道:
>
> On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford
> wrote:
>
>
> Richar
— Jojo
在 2021年8月16日 +0800 PM3:15,Richard Biener ,写道:
> On Fri, Aug 13, 2021 at 3:59 AM Jojo R wrote:
> >
> >
> > — Jojo
> > 在 2021年8月11日 +0800 PM6:44,Richard Biener ,写道:
> >
> > On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford
> > wrote:
> >
> >
> > Richard Biener writes:
> >
> > On Tue, Aug
On Fri, Aug 13, 2021 at 3:59 AM Jojo R wrote:
>
>
> — Jojo
> 在 2021年8月11日 +0800 PM6:44,Richard Biener ,写道:
>
> On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford
> wrote:
>
>
> Richard Biener writes:
>
> On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
> wrote:
>
>
> Some target like RIS
— Jojo
在 2021年8月11日 +0800 PM6:44,Richard Biener ,写道:
> On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford
> wrote:
> >
> > Richard Biener writes:
> > > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
> > > wrote:
> > > >
> > > > Some target like RISC-V allow to group vector register as
Richard Biener writes:
> On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford
> wrote:
>>
>> Richard Biener writes:
>> > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
>> > wrote:
>> >>
>> >> Some target like RISC-V allow to group vector register as a whole,
>> >> and only operate part o
On Wed, Aug 11, 2021 at 11:28 AM Richard Sandiford
wrote:
>
> Richard Biener writes:
> > On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
> > wrote:
> >>
> >> Some target like RISC-V allow to group vector register as a whole,
> >> and only operate part of it in fact, but the 'init-regs' p
Richard Biener writes:
> On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
> wrote:
>>
>> Some target like RISC-V allow to group vector register as a whole,
>> and only operate part of it in fact, but the 'init-regs' pass will add
>> initialization
>> for uninitialized registers. Add this
— Jojo
在 2021年8月10日 +0800 PM7:03,Richard Biener ,写道:
> On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
> wrote:
> >
> > Some target like RISC-V allow to group vector register as a whole,
> > and only operate part of it in fact, but the 'init-regs' pass will add
> > initialization
> > fo
— Jojo
在 2021年8月10日 +0800 PM7:03,Richard Biener ,写道:
> On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
> wrote:
> >
> > Some target like RISC-V allow to group vector register as a whole,
> > and only operate part of it in fact, but the 'init-regs' pass will add
> > initialization
> > fo
On Tue, Aug 10, 2021 at 10:33 AM Jojo R via Gcc-patches
wrote:
>
> Some target like RISC-V allow to group vector register as a whole,
> and only operate part of it in fact, but the 'init-regs' pass will add
> initialization
> for uninitialized registers. Add this hook to reject this action for re
Some target like RISC-V allow to group vector register as a whole,
and only operate part of it in fact, but the 'init-regs' pass will add
initialization
for uninitialized registers. Add this hook to reject this action for reducing
instruction.
gcc/
* init-regs.c (initialize_unini
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