Okay I will take a look at this.
Michael Collison
> On Jun 30, 2017, at 11:04 AM, Andreas Schwab wrote:
>
>> On Jun 23 2017, Michael Collison wrote:
>>
>> diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
>> b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
>> new file mo
On Jun 23 2017, Michael Collison wrote:
> diff --git a/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
> b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
> new file mode 100644
> index 000..e2b020e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/var_shift_mask_1.c
> @@ -0,0
On Fri, Jun 23, 2017 at 10:27:55AM +0100, Michael Collison wrote:
> Fixed the "nitpick" issues pointed out by James. Okay for trunk?
> > I have a few comments below, which are closer to nitpicking than structural
> > issues with the patch.
> >
> > With those fixed, this is OK to commit.
This is
y, June 22, 2017 3:17 AM
To: Michael Collison ; Wilco Dijkstra
; Christophe Lyon ; GCC
Patches ; nd ;
richard.sandif...@linaro.org
Subject: Re: [PATCH] [Aarch64] Variable shift count truncation issues
On Wed, Jun 21, 2017 at 04:42:00PM +0100, Richard Sandiford wrote:
> Michael Collison writes
Subject: Re: [PATCH] [Aarch64] Variable shift count truncation issues
User-Agent: Mutt/1.5.21 (2010-09-15)
On Wed, Jun 21, 2017 at 04:42:00PM +0100, Richard Sandiford wrote:
> Michael Collison writes:
> > Updated the patch per Richard's suggestions to allow scheduling of
> >
; Sent: Thursday, June 15, 2017 6:40 AM
> To: Michael Collison
> Cc: Wilco Dijkstra ; Christophe Lyon
> ; GCC Patches ; nd
>
> Subject: Re: [PATCH] [Aarch64] Variable shift count truncation issues
>
> Michael Collison writes:
>> +(define_insn_and_split "*aar
ginal Message-
From: Richard Sandiford [mailto:richard.sandif...@linaro.org]
Sent: Thursday, June 15, 2017 6:40 AM
To: Michael Collison
Cc: Wilco Dijkstra ; Christophe Lyon
; GCC Patches ; nd
Subject: Re: [PATCH] [Aarch64] Variable shift count truncation issues
Michael Collison w
Michael Collison writes:
> +(define_insn_and_split "*aarch64_reg_3_neg_mask2"
> + [(set (match_operand:GPI 0 "register_operand" "=r")
> + (SHIFT:GPI
> + (match_operand:GPI 1 "register_operand" "r")
> + (match_operator 4 "subreg_lowpart_operator"
> + [(neg:SI (and:SI (match_o
ollison ; GCC Patches
; nd
Subject: Re: [PATCH] [Aarch64] Variable shift count truncation issues
Wilco Dijkstra writes:
> Richard Sandiford wrote:
>
>> Insn patterns shouldn't check can_create_pseudo_p, because there's no
>> guarantee that the associated split happens bef
] [Aarch64] Variable shift count truncation issues
Wilco Dijkstra writes:
> Richard Sandiford wrote:
>
>> Insn patterns shouldn't check can_create_pseudo_p, because there's no
>> guarantee that the associated split happens before RA. In this case
>> it should b
Wilco Dijkstra writes:
> Richard Sandiford wrote:
>
>> Insn patterns shouldn't check can_create_pseudo_p, because there's no
>> guarantee that the associated split happens before RA. In this case it
>> should be safe to reuse operand 0 after RA if you change it to:
>
> The goal is to only create
Richard Sandiford wrote:
> Insn patterns shouldn't check can_create_pseudo_p, because there's no
> guarantee that the associated split happens before RA. In this case it
> should be safe to reuse operand 0 after RA if you change it to:
The goal is to only create and split this pattern before reg
Hi Michael,
On 19 May 2017 at 09:21, Richard Sandiford wrote:
> Thanks for doing this. Just a couple of comments about the .md stuff:
>
> Michael Collison writes:
>> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
>> index 5adc5ed..c6ae670 100644
>> --- a/gcc/config/
Thanks for doing this. Just a couple of comments about the .md stuff:
Michael Collison writes:
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 5adc5ed..c6ae670 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -3999,6 +39
This patch improves code generation for shifts with and operations that can be
omitted based on the size of the operation. AArch64 variable shifts only use the
low 5-6 bits so masking operations that clear higher bits can be removed. When
the shift instructions operate on all register arguments the
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