Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost

2018-08-28 Thread James Greenhalgh
On Mon, Aug 27, 2018 at 10:05:21AM -0500, Luis Machado wrote: > Hi, > > On 08/08/2018 04:46 AM, Siddhesh Poyarekar wrote: > > On 08/01/2018 04:24 AM, James Greenhalgh wrote: > >> OK if this is what is best for your subtarget. > >> > > > > I have pushed this on behalf of Luis since he is on holida

Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost

2018-08-27 Thread Luis Machado
Hi, On 08/08/2018 04:46 AM, Siddhesh Poyarekar wrote: On 08/01/2018 04:24 AM, James Greenhalgh wrote: OK if this is what is best for your subtarget. I have pushed this on behalf of Luis since he is on holiday. Thanks, Siddhesh Similarly to the vector cost changes, we've also noticed a non

Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost

2018-08-08 Thread Siddhesh Poyarekar
On 08/01/2018 04:24 AM, James Greenhalgh wrote: OK if this is what is best for your subtarget. I have pushed this on behalf of Luis since he is on holiday. Thanks, Siddhesh

Re: [PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost

2018-07-31 Thread James Greenhalgh
On Wed, Jul 25, 2018 at 01:35:23PM -0500, Luis Machado wrote: > Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite > failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating > a sbfiz instruction rather than a load with sign extension. > > No performance cha

[PATCH] [AArch64, Falkor] Adjust Falkor's sign extend reg+reg address cost

2018-07-25 Thread Luis Machado
Adjust Falkor's register_sextend cost from 4 to 3. This fixes a testsuite failure in gcc.target/aarch64/extend.c:ldr_sxtw where GCC was generating a sbfiz instruction rather than a load with sign extension. No performance changes. gcc/ChangeLog: 2018-07-25 Luis Machado * config/aarc