On Thu, Mar 10, 2016 at 10:32:15AM -0600, Evandro Menezes wrote:
> >I agree to postpone until GCC 7.
> >
> >[AArch64] Replace insn to zero up SIMD registers
> >
> >gcc/
> >* config/aarch64/aarch64.md
> >(*movhf_aarch64): Add "movi %0, #0" to zero up register.
On 03/10/16 10:27, Evandro Menezes wrote:
On 03/10/16 07:23, James Greenhalgh wrote:
On Wed, Mar 09, 2016 at 03:35:43PM -0600, Evandro Menezes wrote:
On 03/01/16 13:08, Evandro Menezes wrote:
On 03/01/16 13:02, Wilco Dijkstra wrote:
Evandro Menezes wrote:
The meaning of these attributes are
On 03/10/16 07:23, James Greenhalgh wrote:
On Wed, Mar 09, 2016 at 03:35:43PM -0600, Evandro Menezes wrote:
On 03/01/16 13:08, Evandro Menezes wrote:
On 03/01/16 13:02, Wilco Dijkstra wrote:
Evandro Menezes wrote:
The meaning of these attributes are not clear to me. Is there a
reference some
On Wed, Mar 09, 2016 at 03:35:43PM -0600, Evandro Menezes wrote:
> On 03/01/16 13:08, Evandro Menezes wrote:
> >On 03/01/16 13:02, Wilco Dijkstra wrote:
> >>Evandro Menezes wrote:
> >>>The meaning of these attributes are not clear to me. Is there a
> >>>reference somewhere about which insns are FP
On 03/01/16 13:08, Evandro Menezes wrote:
On 03/01/16 13:02, Wilco Dijkstra wrote:
Evandro Menezes wrote:
The meaning of these attributes are not clear to me. Is there a
reference somewhere about which insns are FP or SIMD or neither?
The meaning should be clear, "fp" is a floating point instr
On 03/01/16 13:02, Wilco Dijkstra wrote:
Evandro Menezes wrote:
The meaning of these attributes are not clear to me. Is there a
reference somewhere about which insns are FP or SIMD or neither?
The meaning should be clear, "fp" is a floating point instruction, "simd" a
SIMD one
as defined in A
Evandro Menezes wrote:
>
> The meaning of these attributes are not clear to me. Is there a
> reference somewhere about which insns are FP or SIMD or neither?
The meaning should be clear, "fp" is a floating point instruction, "simd" a
SIMD one
as defined in ARM-ARM.
> Indeed, I had to add the Y
On 02/29/16 12:07, Wilco Dijkstra wrote:
Evandro Menezes wrote:
Please, verify the new "simd" and "fp" attributes for SF and DF.
Both movsf and movdf should be:
(set_attr "simd" "*,yes,*,*,*,*,*,*,*,*")
(set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*")
Did you check that with -mcpu=generic+nos
Evandro Menezes wrote:
>
> Please, verify the new "simd" and "fp" attributes for SF and DF.
Both movsf and movdf should be:
(set_attr "simd" "*,yes,*,*,*,*,*,*,*,*")
(set_attr "fp" "*,*,*,yes,yes,yes,yes,*,*,*")
Did you check that with -mcpu=generic+nosimd you get fmov s0, wzr?
In my version
On 02/26/16 06:37, Wilco Dijkstra wrote:
Evandro Menezes wrote:
I have a question though: is it necessary to add the "fp" and "simd"
attributes to both movsf_aarch64 and movdf_aarch64 as well?
You need at least the "simd" attribute, but providing "fp" as well is clearer
(in principle the TARGE
Evandro Menezes wrote:
>
> I have a question though: is it necessary to add the "fp" and "simd"
> attributes to both movsf_aarch64 and movdf_aarch64 as well?
You need at least the "simd" attribute, but providing "fp" as well is clearer
(in principle the TARGET_FLOAT check in the pattern condition
On 01/22/16 07:52, Wilco Dijkstra wrote:
On 12/16/2015 03:30 PM, Evandro Menezes wrote:
On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
On 20 October 2015 at 00:40, Evandro Menezes
wrote:
In the existing targets, it seems that it's always faster to zero
up a DF
On 12/16/2015 03:30 PM, Evandro Menezes wrote:
>
> On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
>
> On 20 October 2015 at 00:40, Evandro Menezes
>wrote:
>
> In the existing targets, it seems that it's always faster to zero
>up a DF
>
> register with "movi %d0,
On 12/16/2015 03:30 PM, Evandro Menezes wrote:
On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
On 20 October 2015 at 00:40, Evandro Menezes
wrote:
In the existing targets, it seems that it's always faster to zero up
a DF
register with "movi %d0, #0" instead of "fmov %d0, xzr".
This patch mod
On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
On 20 October 2015 at 00:40, Evandro Menezes wrote:
In the existing targets, it seems that it's always faster to zero up a DF
register with "movi %d0, #0" instead of "fmov %d0, xzr".
This patch modifies the respective pattern.
Hi Evandro,
This
On 11/09/2015 04:59 PM, Evandro Menezes wrote:
Hi, Marcus.
Have you an update from the architecture folks about this?
Thank you,
Marcus?
--
Evandro Menezes
On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
On 20 October 2015 at 00:40, Evandro Menezes wrote:
In the existing targets, it seems that it's always faster to zero up a DF
register with "movi %d0, #0" instead of "fmov %d0, xzr".
This patch modifies the respective pattern.
Hi Evandro,
This
Hi, Marcus.
Have you an update from the architecture folks about this?
Thank you,
--
Evandro Menezes
On 10/30/2015 05:24 AM, Marcus Shawcroft wrote:
On 20 October 2015 at 00:40, Evandro Menezes wrote:
In the existing targets, it seems that it's always faster to zero up a DF
register with "m
On 20 October 2015 at 00:40, Evandro Menezes wrote:
> In the existing targets, it seems that it's always faster to zero up a DF
> register with "movi %d0, #0" instead of "fmov %d0, xzr".
>
> This patch modifies the respective pattern.
Hi Evandro,
This patch changes the generic, u architecture i
Ping.
--
Evandro Menezes
On 10/20/2015 09:27 AM, Andrew Pinski wrote:
On Tue, Oct 20, 2015 at 7:59 AM, Andrew Pinski wrote:
On Tue, Oct 20, 2015 at 7:51 AM, Andrew Pinski wrote:
On Tue, Oct 20, 2015 at 7:40 AM, Evandro Menezes wrote:
In the existing targets, it seems that it's always fast
On Tue, Oct 20, 2015 at 7:59 AM, Andrew Pinski wrote:
> On Tue, Oct 20, 2015 at 7:51 AM, Andrew Pinski wrote:
>> On Tue, Oct 20, 2015 at 7:40 AM, Evandro Menezes
>> wrote:
>>> In the existing targets, it seems that it's always faster to zero up a DF
>>> register with "movi %d0, #0" instead of "
On Tue, Oct 20, 2015 at 7:51 AM, Andrew Pinski wrote:
> On Tue, Oct 20, 2015 at 7:40 AM, Evandro Menezes
> wrote:
>> In the existing targets, it seems that it's always faster to zero up a DF
>> register with "movi %d0, #0" instead of "fmov %d0, xzr".
>
> I think for ThunderX 1, this change will
On Tue, Oct 20, 2015 at 7:40 AM, Evandro Menezes wrote:
> In the existing targets, it seems that it's always faster to zero up a DF
> register with "movi %d0, #0" instead of "fmov %d0, xzr".
I think for ThunderX 1, this change will not make a difference. So I
am neutral on this change.
Thanks,
c96250fec6ec5269a7a661a4c Mon Sep 17 00:00:00 2001
From: Evandro Menezes
Date: Mon, 19 Oct 2015 18:31:48 -0500
Subject: [PATCH] [AArch64] Replace insn to zero up DF register
gcc/
* config/aarch64/aarch64.md
(*movdf_aarch64): Add "movi %d0, #0" to zero up DF register.
---
gcc/co
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