Re: [PATCH][AARCH64]: Invent new regclass - FP low regs.

2012-06-19 Thread Marcus Shawcroft
On 19/06/12 15:03, Tejas Belagod wrote: Hi, The attached patch invents a new register class V0 - V15 that is needed for some lane variants of AdvSIMD instructions that can only take V0 - V15 as their indexed register when working on half-word type. Regression tests are happy. OK? OK /Marcus

[PATCH][AARCH64]: Invent new regclass - FP low regs.

2012-06-19 Thread Tejas Belagod
Hi, The attached patch invents a new register class V0 - V15 that is needed for some lane variants of AdvSIMD instructions that can only take V0 - V15 as their indexed register when working on half-word type. Regression tests are happy. OK? Thanks, Tejas Belagod. ARM. Changelog: 2012-06-19