Hi!
On Tue, Sep 26, 2017 at 10:39:06AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (vsx_xscvdpsp_scalar): Use "ww" constraint
> instead of "f" to allow SFmode to be in traditional Altivec
> registers.
Okay. Thanks,
Segher
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
