On Tue, Jun 11, 2013 at 7:53 PM, Michael Meissner
wrote:
> I needed to rework the sync.md so that it would work correctly with no
> optimization (using SUBREG's at -O0 did not give us the even registers for
> holding PTImode values, so I created a PTImode temporary in load_lockedti and
> store_con
I needed to rework the sync.md so that it would work correctly with no
optimization (using SUBREG's at -O0 did not give us the even registers for
holding PTImode values, so I created a PTImode temporary in load_lockedti and
store_conditionalti, which is normally optimized out.
[gcc]
2013-06-11 Mi
On Wed, May 29, 2013 at 04:29:07PM -0400, David Edelsohn wrote:
> - if (mode == QImode || mode == HImode)
> + /* On power8, we want to use SImode for the operation. On previoius
> systems,
> + use the operation in a subword and shift/mask to get the proper byte or
> + halfword. */
> +
- if (mode == QImode || mode == HImode)
+ /* On power8, we want to use SImode for the operation. On previoius systems,
+ use the operation in a subword and shift/mask to get the proper byte or
+ halfword. */
+ if (TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
+{
+ v
This patch adds support for the byte, half-word, and quad-word atomic memory
operations that were added in ISA 2.07 (i.e. power8). Like the other patches,
this passes bootstrap and had no regressions in make check. Is it ok to commit
this patch after the previous 6 patches have been applied?
[gc
