think Richard's suggestion above should work.
Thanks,
Kyrill
The new patch could build gcc and run gcc regression test
successfully.
Please correct me if I still missing something.
Thanks,
Shiva
-Original Message-
From: Richard Earnshaw [mailto:richard.earns...@foss.arm.com]
Sent: Thu
>>> Because arm/thumb mode use different syntax for strb,
>>>>>>>>> we output the assembly as str%(%)
>>>>>>>>> which will put the condition code in the right place according to
>>>>>>>>> TARGET_UNIFIED_ASM.
>>>>>
turn off this
restriction for Thumb and allow the conditional execution of this.
In any case, I think Richard's suggestion above should work.
Thanks,
Kyrill
The new patch could build gcc and run gcc regression test
successfully.
Please correct me if I still missing something.
Thanks,
Shi
ks,
Kyrill
The new patch could build gcc and run gcc regression test
successfully.
Please correct me if I still missing something.
Thanks,
Shiva
-----Original Message-
From: Richard Earnshaw [mailto:richard.earns...@foss.arm.com]
Sent: Thursday, June 04, 2015 4:42 PM
To: Kyrill Tkachov; Shiva Chen
Cc:
correct me if I still missing something.
Thanks,
Shiva
-----Original Message-
From: Richard Earnshaw [mailto:richard.earns...@foss.arm.com]
Sent: Thursday, June 04, 2015 4:42 PM
To: Kyrill Tkachov; Shiva Chen
Cc: Ramana Radhakrishnan; GCC Patches; ni...@redhat.com; Shiva Chen
Subject: Re: [GCC
ion of this.
In any case, I think Richard's suggestion above should work.
Thanks,
Kyrill
The new patch could build gcc and run gcc regression test
successfully.
Please correct me if I still missing something.
Thanks,
Shiva
-Original Message-----
From: Richard Earnshaw [mailto:richard.earns...@foss.ar
>>>>>>|| model == MEMMODEL_RELEASE)
>>>>>> return \"ldr%?\\t%0, %1\";
>>>>>>else
>>>>>> return \"lda%?\\t%0, %1\";
>>>>>> }
>>>>
or Thumb and allow the conditional execution of this.
In any case, I think Richard's suggestion above should work.
Thanks,
Kyrill
The new patch could build gcc and run gcc regression test successfully.
Please correct me if I still missing something.
Thanks,
Shiva
-----Original Message-----
gcc-patches/2015-06/msg00384.html
>>> to write this in a clean way.
>>>
>>>> Because we already set "predicable" "yes" and predicable_short_it" "no"
>>>> for the pattern.
>>>
>>>
>>> That&
Thumb and allow the conditional execution of this.
In any case, I think Richard's suggestion above should work.
Thanks,
Kyrill
The new patch could build gcc and run gcc regression test successfully.
Please correct me if I still missing something.
Thanks,
Shiva
-Original Message-
Fro
is.
> In any case, I think Richard's suggestion above should work.
>
> Thanks,
> Kyrill
>
>
>>
>> The new patch could build gcc and run gcc regression test successfully.
>>
>> Please correct me if I still missing something.
>>
>> Thanks,
4:42 PM
To: Kyrill Tkachov; Shiva Chen
Cc: Ramana Radhakrishnan; GCC Patches; ni...@redhat.com; Shiva Chen
Subject: Re: [GCC, ARM] armv8 linux toolchain asan testcase fail due to stl
missing conditional code
On 04/06/15 09:17, Kyrill Tkachov wrote:
Hi Shiva,
On 04/06/15 04:13, Shiva Chen wrote:
mething.
Thanks,
Shiva
-Original Message-
From: Richard Earnshaw [mailto:richard.earns...@foss.arm.com]
Sent: Thursday, June 04, 2015 4:42 PM
To: Kyrill Tkachov; Shiva Chen
Cc: Ramana Radhakrishnan; GCC Patches; ni...@redhat.com; Shiva Chen
Subject: Re: [GCC, ARM] armv8 linux toolchain asan tes
On 04/06/15 09:17, Kyrill Tkachov wrote:
> Hi Shiva,
>
> On 04/06/15 04:13, Shiva Chen wrote:
>> Hi, Ramana
>>
>> Currently, I work for Marvell and the company have copyright assignment on
>> file.
>>
>> Hi, all
>>
>> After adding the attribute and rebuild gcc, I got the assembler error message
>
Hi Shiva,
On 04/06/15 04:13, Shiva Chen wrote:
Hi, Ramana
Currently, I work for Marvell and the company have copyright assignment on file.
Hi, all
After adding the attribute and rebuild gcc, I got the assembler error message
load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]'
When i look i
Hi, Ramana
Currently, I work for Marvell and the company have copyright assignment on file.
Hi, all
After adding the attribute and rebuild gcc, I got the assembler error message
load_n.s:39: Error: bad instruction `ldrbeq r0,[r0]'
When i look into armv8 ISA document, it seems ldrb Encoding A1
Hi, Ramana
I'm not sure what copyright assignment means ?
Does it mean the patch have copyright assignment or not ?
I update the patch to add "predicable" and "predicable_short_it"
attribute as suggestion.
However, I don't have svn write access yet.
Shiva
2015-06-03 16:36 GMT+08:00 Kyrill Tk
On 03/06/15 09:32, Ramana Radhakrishnan wrote:
This pattern is not predicable though, i.e. it doesn't have the "predicable" attribute
set to "yes".
Therefore the compiler should be trying to branch around here rather than try
to do a cond_exec.
Why does the generated code above look like it's
Hi Shiva,
On 03/06/15 05:12, Shiva Chen wrote:
Hi,
I noticed that armv8(32 bit target) linux toolchain
run asan testcase would get the following message:
FAIL: c-c++-common/asan/heap-overflow-1.c -O0 output pattern test, is
Executing on host:
/home/gccbuilder-x86/test/mgcc5.0/testsuite/../to
On 03/06/15 05:12, Shiva Chen wrote:
It seems that stl should generate as stlne.
Otherwise, slt will get null reference when r3 is 0.
To fix the issue, add %? when output stl assembly pattern in sync.md.
Please also mark these patterns as predicable.
i.e. (set_attr "predicable" "yes"
Hi,
I noticed that armv8(32 bit target) linux toolchain
run asan testcase would get the following message:
FAIL: c-c++-common/asan/heap-overflow-1.c -O0 output pattern test, is
Executing on host:
/home/gccbuilder-x86/test/mgcc5.0/testsuite/../tools/x86_64/install/bin/qemu-arm
-E
LD_LIBRARY_PAT
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