Re: [BUG FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

2023-11-20 Thread Robin Dapp
LGTM. I prefer that over the iterator. Regards Robin

[BUG FIX] RISC-V: Fix intermediate mode on slide1 instruction for SEW64 on RV32

2023-11-20 Thread Juzhe-Zhong
This bug was discovered on PR112597, with -march=rv32gcv_zvl256b --param=riscv-autovec-preference=fixed-vlmax ICE: bug.c:10:1: error: unrecognizable insn: 10 | } | ^ (insn 10 9 11 2 (set (reg:V4SI 140) (unspec:V4SI [ (unspec:V4BI [ (const_v