Hi Roger,
+(define_insn "si2_cnt16"
+ [(set (match_operand:SI 0 "dest_reg_operand" "=w")
Please use "register_operand", and "r" constraint.
+(ANY_ROTATE:SI (match_operand:SI 1 "register_operand" "c")
Please use "r" constraint instead of "c".
+ (const_int 16)))]
+ "TARGET_SW
On 10/27/23 08:22, Roger Sayle wrote:
This patch improves the code generated by the ARC back-end for CPUs
without a barrel shifter but with -mswap. The -mswap option provides
a SWAP instruction that implements SImode rotations by 16, but also
logical shift instructions (left and right) by 16
This patch improves the code generated by the ARC back-end for CPUs
without a barrel shifter but with -mswap. The -mswap option provides
a SWAP instruction that implements SImode rotations by 16, but also
logical shift instructions (left and right) by 16 bits. Clearly these
are also useful build
