Re: [AArch64] Support float->int conversions in vector registers.

2013-05-01 Thread Marcus Shawcroft
On 01/05/13 16:09, James Greenhalgh wrote: Hi, The fcvt instructions also have forms which leave their integer result as a scalar in the SIMD register set. This patch adds those alternatives for the lceil family of standard patterns. Regression tested on aarch64-none-elf with no regressions.

[AArch64] Support float->int conversions in vector registers.

2013-05-01 Thread James Greenhalgh
Hi, The fcvt instructions also have forms which leave their integer result as a scalar in the SIMD register set. This patch adds those alternatives for the lceil family of standard patterns. Regression tested on aarch64-none-elf with no regressions. Thanks, James --- 2013-05-01 James Greenha