h64/tsv110.md: New file.
Thanks,
wuyuan
-邮件原件-
发件人: James Greenhalgh [mailto:james.greenha...@arm.com]
发送时间: 2019年4月4日 1:58
收件人: wuyuan (E)
!
Best Regards,
wuyuan
-邮件原件-
发件人: wuyuan (E)
发送时间: 2019年3月15日 21:57
收件人: 'James Greenhalgh'
抄送: Kyrill Tkachov ; gcc-patches@g
!
Best Regards,
wuyuan
-邮件原件-
发件人: wuyuan (E)
发送时间: 2019年3月15日 21:57
收件人: 'James Greenhalgh'
抄送: Kyrill Tkachov ; gcc-patches@g
uot;tsv110_neon_ld4_reg" 11
+ (and (eq_attr "tune" "tsv110")
+ (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\
+ neon_load4_one_lane,neon_load4_one_lane_q"))
+ "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2
,
wuyuan
-邮件原件-
发件人: wuyuan (E)
发送时间: 2019年3月4日 21:46
收件人: 'James Greenhalgh'
抄送: 'Kyrill Tkachov' ; 'gcc-patches@gcc.gnu.org'
; Zhangyichao (AB) ;
Zhanghaijian (A)
.
Best Regards,
wuyuan
-邮件原件-
发件人: wuyuan (E)
发送时间
quot;)
+ (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\
+ neon_load4_one_lane,neon_load4_one_lane_q"))
+ "(tsv110_ls1 + tsv110_fsu1)|(tsv110_ls1 + tsv110_fsu2)|(tsv110_ls2 +
tsv110_fsu1)|(tsv110_ls2 + tsv110_fsu2)")
+
+(define_in
Hi Kyrill:
The gcc 7.3.0 does not discard the store1 and load1 command; I did not
expect the community's latest gcc changes so large .
now I downloaded the latest GCC code, put the patch into GCC source
code, the compiler can pass, thank you very much for your work!
ls2*8)|(tsv110_fsu1*8)|(tsv110_fsu2*8))")
+
+(define_insn_reservation
+ "tsv110_neon_ld4_reg" 11
+ (and (eq_attr "tune" "tsv110")
+ (eq_attr "type" "neon_load4_all_lanes,neon_load4_all_lanes_q,\
+ neon_load4_one_lane,neon_load4_one_lane_q&quo
-邮件原件-
发件人: wuyuan (E)
发送时间: 2018年12月20日 14:06
收件人: 'Ramana Radhakrishnan' ;
'gcc-patches@gcc.gnu.org'
抄送: Zhanghaijian (A) ; Zhangyichao (AB)
; Yangfei (Felix) ;
'ni...@redhat.com' ; 'Richard Earnshaw'
;
Hi Ramana,
Please ignore the patch in the previous email attachment (the
ChangeLog has deleted in this patch..) I have already communicated with Shao
Kun, he has fixed the problem of the previous patch. So I resubmitted the
tsv110 pipeline patch, please review.
The patch as
eon_load4_one_lane_q"))
+ "((tsv110_ls1*8)|(tsv110_ls2*8)|(tsv110_fsu1*8)|(tsv110_fsu2*8))")
+
+(define_insn_reservation
+ "tsv110_neon_ld4_reg" 11
+ (and (eq_attr "tune" "tsv110")
+ (eq_attr "type" "neon_load4_all_lanes,n
tinue to modify.
Thinks
-邮件原件-
发件人: Kyrill Tkachov [mailto:kyrylo.tkac...@foss.arm.com]
发送时间: 2018年12月6日 20:37
收件人: wuyuan (E) ; gcc-patches
Hi ARM maintainers:
The taishanv110 core uses generic pipeline scheduling, which restricted
the performance of taishanv110 core. By adding the pipeline scheduling of
taishanv110 core in GCC,The performance of taishanv110 has been improved.
The patch as follows, please join.
dif
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