Thanks for the review and Commit.
Regards,
Bruce
-邮件原件-
发件人: Richard Sandiford [mailto:richard.sandif...@arm.com]
发送时间: 2020年8月3日 23:40
收件人: bule
抄送: gcc-patches@gcc.gnu.org
主题: Re: [PATCH PR96366][AARCH64] Add support for unpacked vector sub
bule writes:
> Hi,
>
> The tes
Hi,
The test case bb-slp-20.c in the gcc testsuit will cause an ICE in the expand
pass due to the lack of a pattern for subtraction of the VNx2SI mode. I think
the problem has been fully discussed on PR 96366.
The attached file is the patch to solve this problem. Bootstrapped and tested
on aa
Hi,
I reported a PR in gcc Bugzilla about the medium code model in aarch64. A
solution is proposed and some discussion has been posted.
The details of the discussion can be found here :
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95285
Wilco suggest me to make a PIC 48-bit code model by makin
Hi,
I reported a PR in gcc Bugzilla about the medium code model in aarch64. A
solution is proposed and some discussion has been posted.
The details of the discussion can be found here :
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95285
Wilco suggest me to make a PIC 48-bit code model by makin
-邮件原件-
发件人: Martin Jambor [mailto:mjam...@suse.cz]
发送时间: 2020年4月7日 7:21
收件人: bule
抄送: Richard Biener ; gcc-patches@gcc.gnu.org
主题: Re: [AArch64][SVE][IPA] ICE caused by incompatibility of SRA and svst
builtin-function
Hi,
On Thu, Apr 02 2020, Richard Biener wrote:
> On Thu, Ap
void st2_bf16_base (svbfloat16x3_t z1, svbool_t p0, bfloat16_t *x0, intptr_t
x1) {
svst3 (p0, x0, z1);
}
Compiled with -march=armv8.2-a+sve -msve-vector-bits=256 -O2, it will result in
a segment fault in IPA-SRA:
> [bule@localhost gcc10_fail]$ gcc st2_bf16.i -o st2_bf16.s -S
>
