On 5/24/25 11:06 PM, Alexandre Oliva wrote:
In the added C++ testcase, a stack slot at a negative sp offset is
used to hold a value across a call.
There are a couple of causes that directly lead to this outcome:
- the -fstack-clash-protection and -fnon-call-exception options, that
cause arm_f
On 4/19/25 3:29 PM, Denis Chertykov wrote:
Bugfix for PR118591
This bug occurs only with '-Os' option.
The function 'inherit_reload_reg ()' have a wrong condition:
static bool
inherit_reload_reg (bool def_p, int
On 4/11/25 2:29 AM, Uros Bizjak wrote:
Hello!
I would like to backport PR115568 and PR119689 to release branches.
Author: Richard Biener
Date: Wed Apr 9 14:36:19 2025 +0200
rtl-optimization/119689 - compare-debug failure with LRA
The previous change to fix LRA rematerialization b
On 4/9/25 8:40 AM, Richard Biener wrote:
The previous change to fix LRA rematerialization broke compare-debug
for i586 bootstrap. Fixed by using prev_nonnote_nondebug_insn
instead of prev_nonnote_insn.
Bootstrapped on i586-linux where the miscompare is gone with this
patch. Bootstrap and reg
On 3/27/25 7:49 AM, Xi Ruoyao wrote:
I'm proposing the backport to fix an ICE building gegl on powerpc64le:
https://gcc.gnu.org/PR119340. Bootstrapped and regtested on
powerpc64le-linux-gnu, OK for releases/gcc-14?
OK for me. Thank you for working on PR119340.
gcc/lra-constraints.cc
On 3/21/25 9:00 AM, Jakub Jelinek wrote:
Hi!
Here is an updated version of Surya's PR116028 fix from August, which got
reverted because it caused bootstrap failures on aarch64, later on bootstrap
comparison errors there as well and problems on other targets as well.
The changes compared to the
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119270
The patch was successfully bootstrapped and tested on x86_64 and aarch64.
commit 6c443e128802bd93158a3db7c4edf5fc1fc76c8d
Author: Vladimir N. Makarov
Date: Wed Mar 19 16:06:41 2025 -0400
[PR119270][IRA]: Ignor
On 3/18/25 4:38 AM, Jakub Jelinek wrote:
Hi!
The following testcase ICEs starting with r15-3213 in
decompose_normal_address and starting with r15-3288 ICEs
in lra_rtx_hash, which since r8-5466 can't handle SUBREG
(previously SUBREG was "ei" and lra_rtx_hash can handle
that through
val += lra_r
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119285
The patch was successfully bootstrapped and tested on x86_64 and aarch64.
I've checked the patch for SPEC2017 lbm_s on Zen4 and i5-13600k and
don't see performance or code size change anymore.
I also checked whole
The following patch solves performance issue mentioned in
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114991
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le.
commit e355fe414aa3aaf215c7dd9dd789ce217a1b458c
Author: Vladimir N. Makarov
Date: Mon Mar 10 16:26:5
The following patch adds a test for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118940
The PR is actually solved by a patch I submitted this week for another PR.
commit 3071eb2848a2e748cfd67e8c897890ce06c69d06
Author: Vladimir N. Makarov
Date: Thu Feb 27 13:39:04 2025 -0500
[PR118940][
This is a test taken from
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116336
The PR is actually solved a few weeks ago.
commit e59dd301aea9c8d5a5d04e808c87d591a26e85bb
Author: Vladimir N. Makarov
Date: Thu Feb 27 13:05:44 2025 -0500
[PR116336][LRA]: Add a test
Patch for PR11
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119021
The patch was successfully tested and bootstrapped on x86-64.
commit 7ce3a8e872d945d537a7e7ba1bd3f45b1cf9a6d2
Author: Vladimir N. Makarov
Date: Wed Feb 26 11:28:08 2025 -0500
[PR119021][LRA]: Fix rtl correctn
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115458
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
aarch64.
commit 2341f675edadd6370147d2bc55ca7761a7ecfaa1
Author: Vladimir N. Makarov
Date: Tue Feb 25 15:01:15 2025 -0500
[PR115458][LRA
On 2/14/25 12:27 PM, Peter Bergner wrote:
On 2/14/25 10:43 AM, Vladimir Makarov wrote:
The patch is very well described and it is OK for me to commit it into the
trunk. Thank you for working on this issue, Richard.
If we have some new failures on targets I believe the hook has enough
On 2/13/25 11:08 AM, Richard Sandiford wrote:
From 46ad583e65a1c5a27e2203a7571bba6eb0766bc6 Mon Sep 17 00:00:00 2001
From: Richard Sandiford
Date: Fri, 7 Feb 2025 15:40:21 +
Subject: [PATCH] ira: Add new hooks for callee-save vs spills [PR117477]
To: gcc-patches@gcc.gnu.org
Following on
On 2/7/25 12:18 PM, Richard Sandiford wrote:
FWIW, here's a very rough initial version of the kind of thing
I was thinking about. Hopefully the hook documentation describes
the approach. It's deliberately (overly?) flexible.
I've included an aarch64 version that (a) models the fact that the
On 2/6/25 5:35 PM, Jan Hubicka wrote:
Register 3 (first caller saved) has cost 11000. This comes from:
add_cost = ((ira_memory_move_cost[mode][rclass][0]
+ ira_memory_move_cost[mode][rclass][1])
* saved_nregs / hard_regno_nregs (
On 2/6/25 4:54 PM, Richard Sandiford wrote:
Vladimir Makarov writes:
This is a complicated problem resulted in many tries to fix it in some
general way.
In general I am agree with Surya's approach to scale cost of reg
saves/restores somehow. But the general approach, although solved
On 2/3/25 1:20 AM, H.J. Lu wrote:
commit 3b9b8d6cfdf59337f4b7ce10ce92a98044b2657b
Author: Surya Kumari Jangala
Date: Tue Jun 25 08:37:49 2024 -0500
ira: Scale save/restore costs of callee save registers with block frequency
scales the cost of saving/restoring a callee-save hard regist
On 1/28/25 1:11 PM, Surya Kumari Jangala wrote:
Hi,
The following patch has been bootstrapped and regtested on powerpc64le-linux,
aarch64-linux and x86_64-linux. This patch is a proposed fix for PR118533.
Request you to please review the patch.
Regards
Surya
lra: initialize allocated_hard_re
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115568
The patch was successfully bootstrapped and tested on x86-64.
commit 98545441308c2ae4d535f14b108ad6551fd927d5
Author: Vladimir N. Makarov
Date: Wed Feb 5 14:23:23 2025 -0500
[PR115568][LRA]: Use more strict ou
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116234
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le.
commit decc6c0d4d909ce510b6533c48d70d0b353f909a
Author: Vladimir N. Makarov
Date: Fri Jan 31 09:39:45 2025 -0500
[PR116234][LR
The patch in the attachment solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118663
The patch was successfully bootstrapped and tested on ppc64le, x86_64,
aarch64.
commit 01339d29b7663d85eea6145eac2b1ad1da428c11
Author: Vladimir N. Makarov
Date: Tue Jan 28 08:37:33 2025 -0500
[PR11
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118497
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le.
The patch changes cost calculation and in many cases it results in new
testsuite failures on different targets. But I hope it will n
The patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118560
Successfully tested and bootstrapped on x86-64,aarch64,ppc64le.
commit 07f62ed9a7b09951f83855e19d41641b098190b1
Author: Vladimir N. Makarov
Date: Mon Jan 20 17:08:50 2025 -0500
[PR118560][LRA]: Fix typo in checking secon
On 1/18/25 1:19 AM, Denis Chertykov wrote:
Vladimir Makarov writes:
I'd prefer something like the patch in the attachment.
It is simpler and even removing more LRA code than adding one.
But most important, it generates smaller reserved stack space as QI
and TI pseudos will share the
On 1/19/25 2:28 PM, Uros Bizjak wrote:
On Fri, Jan 17, 2025 at 10:01 PM Vladimir Makarov wrote:
This is one more patch to solve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118067
with different -mcpu used.
The patch was successfully bootstrapped and tested on x86-64, aarch64, and
On 1/11/25 1:15 PM, Denis Chertykov wrote:
The fix for PR117868.
In brief:
this is an LRA bug derived from reuse spilling slots after frame
pointer spilling.
The slot was created for QImode (1 byte) and it was reused after
spilling of the
frame pointer for TImode register (16 bytes long) and
This is one more patch to solve
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118067
with different -mcpu used.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le.
commit 9f009e8865cda01310c52f7ec8bdaa3c557a2745
Author: Vladimir N. Makarov
Date: Fri Jan 17 1
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118067
The patch was successfully tested and bootstrapped on x86_64, aarch64,
and ppc64le.
commit d9835825b3d7193b3d6669174f4386be2cb1
Author: Vladimir N. Makarov
Date: Thu Jan 16 12:17:31 2025 -0500
[PR118067
The commit message contains an explanation.
commit 94d8de53388793f4d5fc0d0aa00fef32ca4aa870
Author: Vladimir N. Makarov
Date: Fri Jan 10 10:36:24 2025 -0500
[PR118017][LRA]: Fix test for i686
My previous patch for PR118017 contains a test which fails on i686. The patch fixes this
The patch in the attachment solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118017
The patch was successfully bootstrapped and tested on x86-64 and aarch64.
commit 6ffaed8d8713874b7c4ee112249ed8a91ff9
Author: Vladimir N. Makarov
Date: Thu Jan 9 16:22:02 2025 -0500
[PR118017][LRA
The following patch is for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117248
The first patch variant resulted in PR117999 (new libgo test failures).
The patch was successfully bootstrapped and tested on x86-64.
The patch was also checked for libgo on arm for PR11799.
commit 936058ce9ed159b4
The patch reverses a fix for PR117248 because it adds new failures in
libgo test on arm (PR117999).
I'll fix PR117248 with another patch soon which will not result in PR117999.
commit 1a28ff1c01c290d50fb4ebd6e6a49482195cab9c
Author: Vladimir N. Makarov
Date: Wed Dec 18 13:28:43 2024 -0500
The following patch is a better solution for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116778
The patch was successfully tested and bootstrapped on x86-64, aarch64,
ppc64le.
commit fca0ab08cd936464b152e9b45356f625eba27575
Author: Vladimir N. Makarov
Date: Wed Dec 11 15:36:21 2024 -0500
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117946
The patch was successfully tested and bootstrapped on x86_64, ppc64le,
aarch64.
commit 6fc3da8fa2af1d4ee154ea803636eabde358b553
Author: Vladimir N. Makarov
Date: Tue Dec 10 12:50:27 2024 -0500
[PR117946][LRA
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117248
I tested the patch extensively on x86-64, aarch64, ppc64le as the patch
contains big changes in live analysis and reg notes update. I hope it
will not result in new PRs.
commit 75e7d1600f47859df40b2ac0feff5a71e0d
The proposed patch can be a fix and you can commit it. The only request
is not to close PR for now.
LRA rematerialization sub-pass rematerializes insn containing only
pseudos assigned to hard regs and should not change live-range of
spilling pseudos. So sentence "Rematerialization sometimes
Sorry, I forgot to add the patch itself. Here it is.
On 11/29/24 15:01, Vladimir Makarov wrote:
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117770
The patch was successfully tested and bootstrapped on x864_64,
aarch64, ppc64le.
commit
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117770
The patch was successfully tested and bootstrapped on x864_64, aarch64,
ppc64le.
On 11/27/24 04:05, Uros Bizjak wrote:
Hello!
I'd like to backport two LRA patches to gcc-14 branch:
1. [PR114942][LRA]: Don't reuse input reload reg of inout early clobber operand
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=9585317f0715699197b1313bbf939c6ea3c1ace6
2. [PR117105][LRA]: Use
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117105
The patch was successfully tested and bootstrapped on x86-64, ppc64le,
aarch64.
commit 4b09e2c67ef593db171b0755b46378964421782b
Author: Vladimir N. Makarov
Date: Mon Nov 25 16:09:00 2024 -0500
[PR117105][LRA]
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116587
The patch was successfully tested and bootstrapped on x86-64, ppc64le,
aarch64.
commit 56fc6a6d9edc9f9170285ef31c7f312608fad88c
Author: Vladimir N. Makarov
Date: Wed Nov 20 14:25:41 2024 -0500
[PR116587][LRA
On 11/13/24 14:10, Denis Chertykov wrote:
The fix for PR117191
Wrong code appears after dse2 pass because it removes necessary insns.
(ie insn 554 - store to frame spill slot)
This happened because LRA pass doesn't cleanup the code exactly like
reload does.
The reload1.c has a special pass f
On 10/10/24 14:32, Denis Chertykov wrote:
The patch is very simple.
On x86_64, it bootstraps+regtests fine.
Ok for trunk?
Sorry for the delay with the answer. I missed your patch and pinging it
was the right thing to do.
Thanks for the detail explanation of the problem which makes me easy
On 8/22/24 04:44, Richard Sandiford wrote:
The sequence of events in this PR is that:
- the function has many addresses in which only a single hard base
register is acceptable. Let's call the hard register H.
- IRA allocates that register to one of the pseudo base registers.
Let's call
On 8/11/24 21:50, Kewen.Lin wrote:
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 92b343fa99a..f355c6c6168 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -4742,7 +4742,9 @@ curr_insn_transform (bool check_only_p)
}
*loc = new_reg
On 8/9/24 17:00, Peter Bergner wrote:
On 8/9/24 12:02 PM, Vladimir Makarov wrote:
I believe your should reverse the original patch and all the patches you
submitted to fix the issues with the original patch.
I agree this commit should be reverted and Kyrill has pushed that already,
so
On 8/9/24 05:49, Kewen.Lin wrote:
Hi,
Commit r15-2084 exposes one ICE in LRA. Firstly, before
r15-2084 KFmode has 126 bit precision while V1TImode has 128
bit precision, so the subreg (subreg:V1TI (reg:KF 131) 0) is
paradoxical_subreg_p, which stops some passes from doing
some optimization.
On 8/9/24 08:58, Surya Kumari Jangala wrote:
I am looking into this failure.
Sorry for delay with this email. I was on vacation.
I believe your should reverse the original patch and all the patches you
submitted to fix the issues with the original patch.
This is a standard procedure in s
On 6/14/24 07:10, user202...@protonmail.com wrote:
This patch was inspired from PR 110137. It reduces the amount of stack spilling
by ensuring that more values are constant across a pure function call.
It does not add any new flag; rather, it makes the optimizer generate more
optimal code.
On 5/30/24 03:59, Richard Sandiford wrote:
Tested on aarch64-linux-gnu & x86_64-linux-gnu. OK to install?
Yes. Thank you, Richard.
gcc/
PR rtl-optimization/115281
* ira-conflicts.cc (go_through_subreg): Use the natural size of
the inner mode rather than the outer m
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013
Successfully tested and bootstrapped on x86-64.
commit 44430ef3d8ba75692efff5f6969d5610134566d3
Author: Vladimir N. Makarov
Date: Mon May 13 10:12:11 2024 -0400
[PR115013][LRA]: Modify register starvation recog
The following patch solves
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114942
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
aarch64.
commit 9585317f0715699197b1313bbf939c6ea3c1ace6
Author: Vladimir N. Makarov
Date: Fri May 10 09:15:50 2024 -0400
[PR114942][LRA]
On 5/8/24 23:25, Li, Pan2 wrote:
Hi Vladimir,
Looks this patch results in some ICE in the rvv.exp of RISC-V backend,
feel free to ping me if more information is needed for reproducing.
= Summary of gcc testsuite =
| # of unexpected case / # of unique unexpected case
|gcc |
The following patch is a fix for PR114810 from LRA side.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le.
commit dc859c1fcb6f3ad95022fb078c040907ef361e4c
Author: Vladimir N. Makarov
Date: Wed May 8 10:39:04
On 5/7/24 23:01, Lehua Ding wrote:
Hi Vladimir,
I'll send V3 patchs based on these comments. Note that these four
patches only support subreg liveness tracking and apply to IRA and LRA
pass. Therefore, no performance changes are expected before we support
subreg coalesce. There will be new
On 2/3/24 05:50, Lehua Ding wrote:
This patch apply the DF_LIVE_SUBREG to LRA pass. More changes were made
to the LRA than the IRA since the LRA will modify the DF data directly.
The main big changes are centered on the lra-lives.cc file.
gcc/ChangeLog:
* lra-coalesce.cc (update_live_i
On 2/3/24 05:50, Lehua Ding wrote:
This patch simple replace df_get_live_in to df_get_subreg_live_in
and replace df_get_live_out to df_get_subreg_live_out.
gcc/ChangeLog:
* ira-build.cc (create_bb_allocnos): Switch to DF_LIVE_SUBREG df data.
(create_loop_allocnos): Ditto.
I am resending this message as the previous one had one wrong response
email address "gcc-pat...@gcc.gnu.org"
Forwarded Message
Subject: Re: [PATCH V2 0/4] Add DF_LIVE_SUBREG data and apply to IRA
and LRA
Date: Wed, 1 May 2024 08:35:27 -0400
From: Vladimir M
On 4/29/24 08:59, Wilco Dijkstra wrote:
According to documentation, '^' should only have an effect during reload.
However ira-costs.cc treats it in the same way as '?' during early costing.
As a result using '^' can accidentally disable valid alternatives and cause
significant regressions (see
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114415
The patch was successfully tested and bootstrapped on x86_64, ppc64le,
aarch64.
commit fe305ca39930afc301cdd1f1143d540d1bfa2a48
Author: Vladimir N. Makarov
Date: Thu Apr 4 16:04:04 2024 -0400
[PR114415][sche
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99829
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
and aarch64.
commit 9c91f8a88b2db50c8faf70786d3cef27b39ac9fc
Author: Vladimir N. Makarov
Date: Tue Mar 19 16:57:11 2024 -0400
[PR99829][L
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113790
The patch was successfully bootstrapped and tested on x86-64,ppc64le,
and aarch64.
commit cebbaa2a84586a7345837f74a53b7a0263bf29ee
Author: Vladimir N. Makarov
Date: Fri Mar 8 14:48:33 2024 -0500
[PR113790][L
On 2/5/24 11:10, Jeff Law wrote:
On 2/5/24 00:01, Lehua Ding wrote:
For SPEC INT 2017, when using upstream GCC (whitout these patches),
I get a
coredump when training the peak case, so no data yet. The cause of
the core
dump still needs to be investigated.
Typo, SPEC INT 2017 -> SPEC FP
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113526
The patch was successfully bootstrapped and tested on x86-64, ppc64le,
and aarch64.
commit 5c617df410602d0e51d61c84d1ae7e9b3f51efa4
Author: Vladimir N. Makarov
Date: Thu Jan 25 14:41:17 2024 -0500
[PR113526]
On 1/15/24 07:56, Maxim Kuvyrkov wrote:
Hi Vladimir,
Hi Jeff,
Richard and Alexander have reviewed this patch and [I assume] have no
further comments. OK to merge?
I trust Richard and Alexander therefore I did not do additional review
of the patches and have no any comment. Richard's or
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113354
The patch was tested on building MIPS target.
The patch was successfully tested and bootstrapped on x86-64, ppc64le,
aarch64.
commit 5f662bce28618ea5417f68a17d5c2d34b052ecb2
Author: Vladimir N. Makarov
Date: Mon
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
The patch was successfully bootstrapped and tested on x86_64, aarch64,
ppc64le
commit 902a5931a1fbb04c65b48ca8b0f3827f6ff3b43e
Author: Vladimir N. Makarov
Date: Thu Jan 11 08:46:26 2024 -0500
[PR112918][LRA]:
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112918
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64.
The patch affects a sensitive part of LRA. So I will monitor that the
commit does not create serious failures on other targets. If
On 12/13/23 16:00, Alex Coplan wrote:
Hi,
In PR112906 we ICE because we try to use force_reg to reload an
auto-increment address, but force_reg can't do this.
With the aim of fixing the PR by supporting reloading arbitrary
addresses in pre-RA splitters, this patch generalizes
lra-constraints.
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112875
The patch was successfully tested and bootstrapped on x86-64 and ppc64le.
commit 48cb51827c9eb991b92014a3f59d31eb237ce03f
Author: Vladimir N. Makarov
Date: Fri Dec 8 15:37:42 2023 -0500
[PR112875][LRA]: Fix an
On 12/7/23 03:39, Jakub Jelinek wrote:
On Thu, Dec 07, 2023 at 09:36:22AM +0100, Jakub Jelinek wrote:
So, one way to fix the LRA issue would be just to use
lra_insn_recog_data_len = index * 3U / 2;
if (lra_insn_recog_data_len <= index)
lra_insn_recog_data_len = index + 1;
basically
On 12/3/23 05:13, Richard Sandiford wrote:
[Gah. In my head I'd sent this a few weeks ago, but it turns out
that I hadn't even got to the stage of writing the changlog...]
LRA keeps track of the biggest mode for both hard registers and
pseudos. The updates assume that the modes are ordered
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112445
The patch was successfully bootstrapped and tested on x86-64, aarch64,
ppc64le.
commit 1390bf52c17a71834a1766c0222e4f8a74efb162
Author: Vladimir N. Makarov
Date: Fri Dec 1 11:46:37 2023 -0500
[PR112445][LRA]:
On 11/22/23 06:14, Maxim Kuvyrkov wrote:
We currently have 3 implementations of print_hard_reg_set()
(all with the same name!) in ira-color.cc, ira-conflicts.cc, and
sel-sched-dump.cc. This patch generalizes implementation in
ira-color.cc, and uses it in all other places. The declaration
is a
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112610
The patch was successfully tested and bootstrapped on x86-64.
commit 95f61de95bbcc2e4fb7020e27698140abea23788
Author: Vladimir N. Makarov
Date: Wed Nov 22 09:01:02 2023 -0500
[IRA]: Fix using undefined dump fi
On 11/16/23 21:06, Lehua Ding wrote:
Hi Vladimir,
Thank you so much for your review. Based on your comments, I feel like
there are a lot of issues, especially the long compile time issue. So
I'm going to reorganize and refactor the patches so that as many of
them as possible can be reviewed
On 11/12/23 07:08, Lehua Ding wrote:
This patch relax the subreg track capability to all subreg registers.
The patch is ok for me when general issues I mentioned in my first email
and the issue given below are fixed.
gcc/ChangeLog:
* ira-build.cc (get_reg_unit_size): New.
(ha
On 11/12/23 07:08, Lehua Ding wrote:
This patch changes the previous way of creating a copy between allocnos to
objects.
gcc/ChangeLog:
* ira-build.cc (find_allocno_copy): Removed.
(find_object): New.
(ira_create_copy): Adjust.
(add_allocno_copy_to_list): Adju
On 11/12/23 07:08, Lehua Ding wrote:
gcc/ChangeLog:
* hard-reg-set.h (struct HARD_REG_SET): New shift operator.
* ira-build.cc (ira_create_object): Adjust.
(find_object): New.
(find_object_anyway): New.
(ira_create_allocno): Adjust.
(get_range):
On 11/12/23 07:08, Lehua Ding wrote:
This patch switch the use of live_reg data to live_subreg data.
gcc/ChangeLog:
* ira-build.cc (create_bb_allocnos): Switch.
Switch to what? Although from the patch itself someone can figure it
out, you should write it in the changelog entry.
On 11/14/23 12:18, Vladimir Makarov wrote:
On 11/14/23 03:38, Lehua Ding wrote:
This is perfectly fine, the code inside the live_subreg problem has a
branch that goes through similar logic to live_reg if it finds no
subreg inside the program. Then when the optimization level is less
On 11/14/23 03:38, Lehua Ding wrote:
This is perfectly fine, the code inside the live_subreg problem has a
branch that goes through similar logic to live_reg if it finds no
subreg inside the program. Then when the optimization level is less
than 2, it doesn't track the subreg. By the way,
On 11/14/23 04:03, Richard Biener wrote:
I suggest you farm bugzilla for the compile-time-hog / memory-hog testcases.
I do have a set of "large" testcases. Scanning results points at
PRs 36262, 37448, 39326, 69609 all having RA in the 20% area at
-O0 -g.
It's also a good idea to take say cc1
On 11/12/23 09:52, Richard Sandiford wrote:
SME has various instructions that require aligned register tuples.
However, the associated tuple modes are already widely used and do
not need to be aligned in other contexts. It therefore isn't
appropriate to force alignment in TARGET_HARD_REGNO_MOD
On 11/12/23 07:08, Lehua Ding wrote:
This patch adds a live_subreg problem to extend the original live_reg to
track the liveness of subreg. We will only try to trace speudo registers
who's mode size is a multiple of nature size and eventually a small portion
of the inside will appear to use sub
On 11/12/23 07:08, Lehua Ding wrote:
V3 Changes:
1. fix three ICE.
2. rebase
Hi,
These patchs try to support subreg coalesce feature in
register allocation passes (ira and lra).
I've started review of v3 patches and here is my initial general
criticism of your patches:
* Absence o
On 11/12/23 07:01, Lehua Ding wrote:
Thanks for the specint performance data. I'll do my best to get the
compile time and memory issues fixed. I'm very curious to know if the
way used to solve the subreg coalesce problem makes sense to you?
If it works, it is ok for me. There is always a r
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112337
The patch was successfully bootstrapped an tested on x86-64, ppc64le,
and aarch64.
commit b3d1d30eeed67c78e223c146a464d2fdd1dde894
Author: Vladimir N. Makarov
Date: Fri Nov 10 11:14:46 2023 -0500
[IRA]: Check
On 11/7/23 22:47, Lehua Ding wrote:
Lehua Ding (7):
ira: Refactor the handling of register conflicts to make it more
general
ira: Add live_subreg problem and apply to ira pass
ira: Support subreg live range track
ira: Support subreg copy
ira: Add all nregs >= 2 pseudos to t
This is one more patch for
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110215
The patch was successfully tested and bootstrapped on x86-64, aarch64,
ppc64le.
commit df14f1c0582cd6742a37abf3a97f4c4bf0caf864
Author: Vladimir N. Makarov
Date: Thu Nov 9 08:51:15 2023 -0500
[IRA]: Fixing
On 10/31/23 18:51, Edwin Lu wrote:
genattr.cc currently generates insn-attr.h with the following structure:
#if CPU_UNITS_QUERY
extern int get_cpu_unit_code (const char *);
extern int cpu_unit_reservation_p (state_t, int);
#endif
extern bool insn_has_dfa_reservation_p (rtx_insn *);
however ge
The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111971
Successfully bootstrapped and tested on x86-64, aarch64, pp64le.
commit df111406b4ea1fe2890e94d51655e571cf260d29
Author: Vladimir N. Makarov
Date: Tue Oct 31 10:54:43 2023 -0400
[RA]: Fixing LRA cycling for mu
The following patch fixes i686 bootstrap failure because of my recent
patch:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112107
commit 7361b49d7fa3624cb3f1f825a22607d9d31986e5
Author: Vladimir N. Makarov
Date: Fri Oct 27 14:50:40 2023 -0400
[RA]: Fixing i686 bootstrap failure because o
The following patch fixes one aarch64 GCC test failure resulted from my
previous patch dealing with reg equivalences.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
ppc64le.
commit 9b03e1d20c00dca215b787a5e959db473325b660
Author: Vladimir N. Makarov
Date: Fri Oct 27
On 10/27/23 09:56, Christophe Lyon wrote:
Hi Vladimir,
On Thu, 26 Oct 2023 at 16:00, Vladimir Makarov wrote:
This is the second attempt to improve RA cost calculation for pseudos
with equivalences. The patch explanation is in the log message.
The patch was successfully bootstrapped and
This is the second attempt to improve RA cost calculation for pseudos
with equivalences. The patch explanation is in the log message.
The patch was successfully bootstrapped and tested on x86-64, aarch64,
and ppc64le. The patch was also benchmarked on x86-64 spec2017.
specfp2017 performance
On 10/18/23 09:37, Richard Sandiford wrote:
Vlad, is it OK if I backport the patch below to fix
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111528 ? Jakub has
given a conditional OK on irc.
Ok. It should be safe. I don't expect any issues because of this.
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