The test at pr116258.c fails on big endian targets,
this is because the test checks that the index of a floating
point multiply is 0, which is correct only for little endian.
gcc/testsuite/ChangeLog:
PR tree-optimization/116258
* gcc.target/aarch64/pr116258.c:
Alter test t
__ARM_NEON_SVE_BRIDGE.
On 6/6/24 13:20, Richard Sandiford wrote:
> Richard Ball writes:
>> __ARM_NEON_SVE_BRIDGE was missed in the original patch and is
>> added by this patch.
>>
>> Ok for trunk and a backport into gcc-14?
>>
>> gcc/ChangeLog:
&
The CASE_VECTOR_SHORTEN_MODE query is missing some equals signs
which causes suboptimal codegen due to missed optimisation
opportunities. This patch also adds a test for thumb2
switch statements as none exist currently.
gcc/ChangeLog:
PR target/115353
* config/arm/arm.h (enum arm_a
__ARM_NEON_SVE_BRIDGE was missed in the original patch and is
added by this patch.
Ok for trunk and a backport into gcc-14?
gcc/ChangeLog:
* config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins):
Add missing __ARM_NEON_SVE_BRIDGE.diff --git a/gcc/config/aarch64/aarch64-c.cc b
Hi,
Requesting permission to backport:
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=24cf1f600b8ad34c68a51f48884e72d01f729893
to gcc-13 in order to fix:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111882
Applies cleanly and with no regressions.
Thanks,
Richard
Hi,
Requesting permission to backport:
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=912753cc5f18d786e334dd425469fa7f93155661
to fix the issue listed here:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114672
in gcc-12 and gcc-13.
Thanks,
Richard
Hi Richard,
I committed this combined patch (with Cortex-A520) for trunk
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=cab53aae43cf94171b01320c08302e47a5daa391
Am I ok to commit just the Cortex-A510 half into gcc-12 and gcc-13.
Thanks,
Richard Ball
From
Regards,
Richard Ball
From: Torbjorn SVENSSON
Sent: 25 April 2024 12:47
To: Richard Ball ; gcc-patches@gcc.gnu.org
; Richard Earnshaw ; Richard
Sandiford ; Marcus Shawcroft
; Kyrylo Tkachov
Subject: Re: [PATCH] arm: Zero/Sign extends for CMSE security
Hi,
On
This patch makes the following changes:
1) When calling a secure function from non-secure code then any arguments
smaller than 32-bits that are passed in registers are zero- or sign-extended.
2) After a non-secure function returns into secure code then any return value
smaller than 32-bits t
When using LTO, handling the pragma for sme before the pragma
for the neon-sve-bridge caused the following error on svset_neonq,
in the neon-sve-bridge.c test.
error: ACLE function '0' can only be called when SME streaming mode is enabled.
This has been resolved by changing the pragma handlers to
Hi all,
Adding the NEON-SVE bridge intrinsics that were missed
in the last patch.
Thanks,
Richarddiff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index
9fd224c1df3f05eadcedaaa41c0859e712b93b78..df63af48298564de9c35bab1dd35891c2581e3d6
100644
--- a/htdocs/gcc-14/changes.html
The SCHEDULER_IDENT for this CPU was incorrectly
set to cortexa55, which is incorrect. This can cause
sub-optimal asm to be generated.
Ok for trunk?
gcc/ChangeLog:
PR target/114272
* config/aarch64/aarch64-cores.def (AARCH64_CORE):
Change SCHEDULER_IDENT from cortexa55 to
The SCHEDULER_IDENT for this CPU was incorrectly
set to cortexa55, which is incorrect. This can cause
sub-optimal asm to be generated.
Ok for trunk?
Can I also backport this to gcc-12 and gcc-13?
gcc/ChangeLog:
PR target/114272
* config/aarch64/aarch64-cores.def (AARCH64_CORE):
When using LTO, handling the pragma for sme before the pragma
for the neon-sve-bridge caused the following error on svset_neonq,
in the neon-sve-bridge.c test.
error: ACLE function '0' can only be called when SME streaming mode is enabled.
Handling the pragmas the other way around fixes this.
No
Adds a check to ensure that the input vector arguments
to a function are not variable length. Previously, only the
output vector of a function was checked.
The ICE in question is within the neon-sve-bridge.c test,
and is related to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111268
gcc/ChangeLog
nuary 2024 17:36
To: Richard Ball
Cc: gcc-patches@gcc.gnu.org ; Richard Sandiford
; Kyrylo Tkachov ; Richard
Earnshaw ; Marcus Shawcroft
Subject: Re: [PATCH] aarch64: Fix ICE in poly-int.h due to SLP.
On Tue, 30 Jan 2024 at 20:13, Richard Ball wrote:
>
> Adds a check to ensure that
Adds a check to ensure that the input vector arguments
to a function are not variable length. Previously, only the
output vector of a function was checked.
gcc/ChangeLog:
* tree-vect-slp.cc (vectorizable_slp_permutation_1):
Add variable-length check for vector input arguments
v2: Formatting and test options fix.
Adds missing bti instruction at the beginning of a virtual
thunk, when bti is enabled.
gcc/ChangeLog:
* config/arm/arm.cc (arm_output_mi_thunk): Emit
insn for bti_c when bti is enabled.
gcc/testsuite/ChangeLog:
* lib/target-supports.
Adds missing bti instruction at the beginning of a virtual
thunk, when bti is enabled.
gcc/ChangeLog:
* config/arm/arm.cc (arm_output_mi_thunk): Emit
insn for bti_c when bti is enabled.
gcc/testsuite/ChangeLog:
* g++.target/arm/bti_thunk.C: New test.diff --git a/gcc/conf
ACLE has added intrinsics to bridge between SVE and Neon.
The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and
SVE vectors.
This patch adds support to GCC for the following 3 intrinsics:
svset_neonq, svget_neonq and svdup_neonq
gcc/ChangeLog:
* config.gcc: Adds ne
Gentle Ping for the patch below:
On 11/9/23 16:14, Richard Ball wrote:
> ACLE has added intrinsics to bridge between SVE and Neon.
>
> The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and
> SVE vectors.
>
> This patch adds support to GCC for the foll
ACLE has added intrinsics to bridge between SVE and Neon.
The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and
SVE vectors.
This patch adds support to GCC for the following 3 intrinsics:
svset_neonq, svget_neonq and svdup_neonq
gcc/ChangeLog:
* config.gcc: Adds ne
Hi all,
Please disregard patch v2, some necessary changes have become apparent after
submission.
I will make these changes and submit as patch v3.
Apologies,
Richard Ball
-Original Message-
From: Richard Ball
Sent: Friday, October 27, 2023 6:18 PM
To: gcc-patches@gcc.gnu.org; Richard
ACLE has added intrinsics to bridge between SVE and Neon.
The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and
SVE vectors.
This patch adds support to GCC for the following 3 intrinsics:
svset_neonq, svget_neonq and svdup_neonq
gcc/ChangeLog:
* config.gcc: Adds ne
v2: Formatting and nits fixed.
Follow up patch to arm: Use deltas for Arm switch tables
This patch moves the switch tables for Arm from the .text section
into the .rodata section.
gcc/ChangeLog:
* config/arm/aout.h: Change to use the Lrtx label.
* config/arm/arm.h (CASE_VECTOR_PC
Follow up patch to arm: Use deltas for Arm switch tables
This patch moves the switch tables for Arm from the .text section
into the .rodata section.
gcc/ChangeLog:
* config/arm/aout.h: Change to use the Lrtx label.
* config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Remove arm targets
For normal optimization for the Arm state in gcc we get an uncompressed
table of jump targets. This is in the middle of the text segment
far larger than necessary, especially at -Os.
This patch compresses the table to use deltas in a similar manner to
Thumb code generation.
Similar code is also use
v2: Add missing PROFILE feature flag.
This patch adds support for the Cortex-A720 CPU to GCC.
No regressions on aarch64-none-elf.
Ok for master?
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-
A720 CPU.
* config/aarch64/aarch64-tune.md: Re
This patch adds support for the Cortex-A720 CPU to GCC.
No regressions on aarch64-none-elf.
Ok for master?
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add Cortex-
A720 CPU.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Do
This patch adds support for the Cortex-A520 CPU to GCC.
No regressions on aarch64-none-elf.
Ok for master?
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Add
Cortex-A520 CPU.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Document
ACLE has added intrinsics to bridge between SVE and Neon.
The NEON_SVE Bridge adds intrinsics that allow conversions between NEON and
SVE vectors.
This patch adds support to GCC for the following 3 intrinsics:
svset_neonq, svget_neonq and svdup_neonq
gcc/ChangeLog:
* config.gcc: Adds n
Thanks Richard,
I've gone through the write access process and committed this.
On 7/31/2023 10:56 AM, Richard Sandiford wrote:
Richard Ball writes:
Add POLY_INT_CST support to code within
fold_ctor_reference. This code previously
only supported INTEGER_CST which caused a
bug when
Prakhar Bahuguna
Giovanni Bajo
Simon Baldwin
+Richard Ball
Scott Bambrough
Wolfgang Bangerth
Gergö Barany
Add POLY_INT_CST support to code within
fold_ctor_reference. This code previously
only supported INTEGER_CST which caused a
bug when using VEC_PERM_EXPR with SVE vectors.
gcc/ChangeLog:
* gimple-fold.cc (fold_ctor_reference):
Add support for Poly_int.
##
Replace manual swapping idiom with std::swap in aarch64.cc
gcc/config/aarch64/aarch64.cc has a few manual swapping idioms of the form:
x = in0, in0 = in1, in1 = x;
The preferred way is using the standard:
std::swap (in0, in1);
We should just fix these to use std::swap.
This will also allow us
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