Hi Kyrill,
> It's been a while, but I believe you had the following comment about
> implementing CSEL:
>
>> (define_insn_and_split "*thumb2_movsicc_insn"
>>[(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
>> (if_then_else:SI
>> @@ -449,17 +473,14 @@
>>
Hi Kyrill,
It's been a while, but I believe you had the following comment about
implementing CSEL:
> (define_insn_and_split "*thumb2_movsicc_insn"
>[(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
> (if_then_else:SI
> @@ -449,17 +473,14 @@
> it\\t%d3
> Hi Omar,
>
> diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
> index 0b00aef7ef7..79cf684e5cb 100644
> --- a/gcc/config/arm/thumb2.md
> +++ b/gcc/config/arm/thumb2.md
> @@ -743,6 +743,9 @@
> if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
>return \"%i
Hi Kyrill,
> -/* Only thumb1 can't support conditional execution, so return true if
> - the target is not thumb1. */
> static bool
>
>
> Functions should have comments in GCC. Can you please write something
> describing the new logic of the function.
>
> arm_have_conditional_execution (void
y use CSEL it falls back to using IT blocks.
Regression tested on arm-none-eabi. The entire patch set was regression
tested on arm-linux-gnueabi also.
That's all folks!
Thanks,
Omar
2020-07-30: Sudakshina Das
Omar Tahir
* config/arm/thumb2.md (*cmovsi_
Omar Tahir
* config/arm/thumb2.md (*thumb2_csneg): New.
(*thumb2_negscc): Don't match if TARGET_COND_ARITH.
* config/arm/arm.md (*if_neg_move): Don't match if
TARGET_COND_ARITH.
gcc/testsuite/ChangeLog:
2020-07-30: Sudakshina Das
Omar Tahir
* config/arm/thumb2.md (*thumb2_csinc): New.
(*thumb2_cond_arith): Generate CINC where possible.
gcc/testsuite/ChangeLog:
2020-07-30: Sudakshina Das
Omar Tahir
* gcc.target/arm/csinc-1.c: New test.
diff --git a/gcc
y match if
!TARGET_COND_ARITH,
otherwise it triggers undesirable combines.
2020-07-30: Sudakshina Das
Omar Tahir
* config/arm/arm.h (TARGET_COND_ARITH): New macro.
* config/arm/arm.c (arm_have_conditional_execution): Return
be
necessary to correctly prioritise conditional instructions over branches in
the rest of this patch series.
Regression tested on arm-none-eabi.
gcc/ChangeLog:
2020-07-30: Omar Tahir
* config/arm/arm-cpus.in (armv8.1-m.main): Tune for Cortex-M55.
diff --git a/gcc/config/arm
Hi all,
This patch series provides support for the following instructions that were
added in Armv8.1-M Mainline [1]:
- CSEL
- CSET
- CSETM
- CSNEG
- CSINV
- CSINC
- CINC
The patch serie
> Omar Tahir writes:
> > Hi Richard,
> >
> > From: Richard Sandiford
> >> > @@ -3719,6 +3722,7 @@ static unsigned int rest_of_handle_sched (void)
> >> > { #ifdef INSN_SCHEDULING
> >> > + first_moveable_pseudo = last
Hi Richard,
From: Richard Sandiford
> > @@ -3719,6 +3722,7 @@ static unsigned int rest_of_handle_sched (void)
> > { #ifdef INSN_SCHEDULING
> > + first_moveable_pseudo = last_moveable_pseudo;
> >if (flag_selective_scheduling
> >&& ! maybe_skip_selective_scheduling ())
> > run_se
her, deeper bug?
Bootstrapped and regression tested on aarch64-none-linux-gnu.
I don't have write privileges, so if it's fine could someone push for me?
Thanks,
Omar
gcc/ChangeLog:
2020-06-30: Omar Tahir
* sched-rgn.c: Include ira-int.h, ira.h, regs.h.
s BTI
instructions are ignored on unsupported architecture versions.
I don't have write access, so could someone commit for me?
Bootstrapped and tested on aarch64 with no regressions.
gcc/ChangeLog:
2020-06-29 Omar Tahir omar.ta...@arm.com
* config/aarch64/aarch64.c (aarch64_asm_trampolin
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